公开(公告)号：US20250075309A1

公开(公告)日：2025-03-06

申请号：US18799515

申请日：2024-08-09

Applicant: Applied Materials, Inc.

Inventor： Jianxin LEI ,  Kirankumar Neelasandra SAVANDAIAH ,  Andrew MOE ,  Madan Kumar SHIMOGA MYLARAPPA

IPC: C23C14/34

Abstract: The disclosure relates to a target for physical vapor deposition processes. In one embodiment, a physical vapor deposition (PVD) target, includes a monolithic target with a support region partially defined by a process face and radial sidewalls; and a recess within a mounting face of the monolithic target, the recess disposed opposite the process face and extending radially outward of the radial sidewalls.

公开(公告)号：US12243774B2

公开(公告)日：2025-03-04

申请号：US17853150

申请日：2022-06-29

Applicant: Applied Materials, Inc.

Inventor： Rui Li ,  Xiangjin Xie ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen

IPC: H01L21/44 ,  C23C16/34 ,  C23C16/455 ,  H01L21/768

Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

公开(公告)号：US12242789B2

公开(公告)日：2025-03-04

申请号：US18439287

申请日：2024-02-12

Applicant: Applied Materials, Inc.

Inventor： Tamer Coskun ,  Aidyn Kemeldinov ,  Chung-Shin Kang ,  Uwe Hollerbach ,  Thomas L. Laidig

IPC: G06F30/39 ,  G06F30/392 ,  G06N20/00 ,  H01L21/68

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

公开(公告)号：US20250068195A1

公开(公告)日：2025-02-27

申请号：US18828621

申请日：2024-09-09

Applicant: Applied Materials, Inc.

Inventor： Wolfgang R. ADERHOLD ,  Abhilash J. MAYUR ,  Yi WANG

IPC: G05D23/19 ,  F27B17/00 ,  G01J5/34 ,  G05B13/02 ,  G05D23/27 ,  G06N20/00 ,  H01L21/66 ,  H05B1/02 ,  H05B3/00

Abstract: Aspects of the present disclosure relation to systems, methods, and apparatus for correcting thermal processing of substrates. In one aspect, a corrective absorption factor curve having a plurality of corrective absorption factors is generated.

公开(公告)号：US20250067937A1

公开(公告)日：2025-02-27

申请号：US18812575

申请日：2024-08-22

Applicant: Applied Materials, Inc.

Inventor： Michael Alexander WEINSTEIN ,  Rutger MEYER TIMMERMAN THIJSSEN

IPC: F21V8/00 ,  G02B27/01

Abstract: The present disclosure generally provides waveguide combiners and methods thereof. The waveguide combiners include a substrate. A first grating is disposed over the substrate. The first grating includes a first device structure. A first coating layer is disposed over the first device structure. A first donor substrate is disposed over the first coating layer. A second grating is disposed over the substrate. The second grating includes a second device structure. A second coating layer is disposed over the second device structure. A second donor substrate is disposed over the second coating layer. An encapsulation layer is disposed over the first grating and the second grating.

公开(公告)号：US12237406B2

公开(公告)日：2025-02-25

申请号：US17082570

申请日：2020-10-28

Applicant: Applied Materials, Inc.

Inventor： Soo Young Choi ,  Beom Soo Park ,  Yi Cui ,  Tae Kyung Won ,  Dong-Kil Yim

IPC: H01L29/786 ,  H01L21/02 ,  H01L23/31 ,  H01L29/66

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

公开(公告)号：US12236575B2

公开(公告)日：2025-02-25

申请号：US17492905

申请日：2021-10-04

Applicant: Applied Materials, Inc.

Inventor： Yangyang Sun ,  Jinxin Fu ,  Kazuya Daito ,  Ludovic Godet

IPC: G06T7/00 ,  G01J1/42 ,  G01J1/44 ,  G01N21/958 ,  G02B27/01 ,  G06T7/80 ,  G06T7/90 ,  H04N23/56 ,  H04N23/74 ,  H04N23/90

Abstract: Embodiments of the present disclosure relate to optical devices for augmented, virtual, and/or mixed reality applications. In one or more embodiments, an optical device metrology system is configured to measure a plurality of first metrics and one or more second metrics for optical devices, the one or more second metrics including a display leakage metric.

公开(公告)号：US20250063716A1

公开(公告)日：2025-02-20

申请号：US18781132

申请日：2024-07-23

Applicant: Applied Materials, Inc.

Inventor： Zhijun CHEN ,  Fredrick FISHBURN

IPC: H10B12/00

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a stacked semiconductor structure is provided, where the stacked semiconductor structure includes a plurality of unit stacks formed on a substrate. Each unit stack has a semiconductor layer, a first dielectric layer, a first gate electrode, and a second dielectric layer of a capacitor portion. A lateral recess of the capacitor portion is open to a first opening through the unit stack. The method includes conformally depositing, in the lateral recess, a doped silicon layer on a lateral end of the semiconductor layer, performing a thermal annealing process after forming the doped silicon layer on the second lateral end. The method further includes forming a capacitor where the lateral recess was disposed, the capacitor contacting the doped silicon layer on the second lateral end of the semiconductor layer.

公开(公告)号：US20250062123A1

公开(公告)日：2025-02-20

申请号：US18235249

申请日：2023-08-17

Applicant: Applied Materials, Inc.

Inventor： SHASHANK SHARMA ,  KAI B. NG ,  NORMAN TAM ,  YUQI GUO ,  ANDY LO ,  HUIXIONG DAI ,  KHOI PHAN ,  CHIHAN HSU ,  MADHUR SACHAN ,  NASRIN KAZEM ,  ZHENXING HAN

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

Abstract: Embodiments disclosed herein include a method of thermal treatment or radical species treatment of a photoresist a metal-oxide photoresist. In an embodiment, a method of patterning a metal-oxide photoresist, such as a Sn-based photoresist, includes depositing the metal-oxide photoresist over a substrate, exposing the metal-oxide photoresist with an extreme ultra-violet (EUV) exposure to form exposed regions and non-exposed regions, developing the exposed metal-oxide photoresist, and performing a thermal treatment and/or a radical species treatment of the metal-oxide photoresist.

公开(公告)号：US12232299B2

公开(公告)日：2025-02-18

申请号：US17964668

申请日：2022-10-12

Applicant: Applied Materials, Inc.

Inventor： Robert Irwin Decottignies ,  Roger Bradford Fish ,  Steven Szudarski ,  Shane Lawrence Kintner

IPC: H05K7/20 ,  H01L21/67

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, an apparatus for processing a substrate comprises a process chamber configured to process a substrate, a substrate support comprising a heat sink configured to cool the substrate support during operation and a water trap panel comprising a pumping ring configured to cool the water trap panel such that the water trap panel condenses water vapor molecules and drops a process chamber pressure during operation, and a chiller operably coupled to the substrate support and configured to supply a cooling fluid to the substrate support via a cooling fluid line that connects to the heat sink and the pumping ring via a serial configuration or a parallel configuration.