公开(公告)号：US06534326B1

公开(公告)日：2003-03-18

申请号：US10099186

申请日：2002-03-13

Applicant: Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

Inventor： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

IPC: H01L2100

CPC classification number: H01L28/56 ,  G11C13/0007 ,  G11C2213/31 ,  H01L21/28291 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.

Abstract translation: 描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层 绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。 还描述了形成多晶存储器结构的方法。 沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。 绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

公开(公告)号：US06462366B1

公开(公告)日：2002-10-08

申请号：US09481674

申请日：2000-01-12

Applicant: Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

Inventor： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

IPC: H01L2976

CPC classification number: H01L29/6684 ,  H01L29/78391

Abstract: A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of &dgr;, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p-well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2&dgr;; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2≧L1+2&dgr;, wherein &dgr; is the alignment tolerance of the lithographic process.

Abstract translation: 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对所述结构进行金属化。铁电存储晶体管包括其中形成有p阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta，其中Δ是光刻工艺的对准公差。

公开(公告)号：US06399521B1

公开(公告)日：2002-06-04

申请号：US09316646

申请日：1999-05-21

Applicant: Fengyan Zhang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Sheng Teng Hsu

IPC: H01L2131

CPC classification number: H01L21/28291 ,  H01L21/28568 ,  H01L28/75 ,  H01L29/513 ,  H01L29/516 ,  H01L29/78391

Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, and piezoelectric transducers. A method for forming an Ir—M—O composite film barrier layer with an oxidized refractory metal barrier layer is also provided.

Abstract translation: 已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜有效防止氧气扩散，并且在氧气环境中耐高温退火。 当与通过氧化相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 即使在氧气中，Ir组合膜在高温退火过程中也保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/阻挡结构可用于非易失性MFMIS（金属/铁/金属/绝缘体/硅）存储器件，DRAM，电容器，热释电红外传感器，光学显示器和压电换能器。 还提供了一种用于形成具有氧化的难熔金属阻挡层的Ir-M-O复合膜阻挡层的方法。

公开(公告)号：US06372034B1

公开(公告)日：2002-04-16

申请号：US09687827

申请日：2000-10-12

Applicant: Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

Inventor： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC: H01L2122

CPC classification number: H01L21/31691

Abstract: A method of preparing a PGO solution for spin coating includes preparing a 2-methoxyethanol organic solvent; adding Pb(OCH3CO)2.3H2O to the organic solvent at ambient temperature and pressure in a nitrogen-filled glaved box to form Pb in methoxyethanol; refluxing the solution in a nitrogen atmosphere at 150° C. for at least two hours; fractionally distilling the refluxed solution at approximately 150° C. to remove all of the water from the solution; cooling the solution to room temperature; determining the Pb concentration of the solution; adding the 2-methoxyethanol solution to the Pb 2-methoxyethanol until a desired Pb concentration is achieved; combining Ge(OR)4, where R is taken the group of Rs consisting of CH2CH3 and CH(CH3)2, and 2-methoxyethanol; and adding Ge(OR)4 2-methoxyethanol to PbO 2-methoxyethanol to form the PGO solution having a predetermined metal ion concentration and a predetermined Pb:Ge molar ration.

Abstract translation: 制备用于旋涂的PGO溶液的方法包括制备2-甲氧基乙醇有机溶剂; 在环境温度和压力下，在氮气充填的玻璃箱中加入Pb（OCH 3 CO）2.3H 2 O至有机溶剂中以在甲氧基乙醇中形成Pb; 将溶液在氮气气氛中在150℃下回流至少2小时; 在大约150℃下将回流的溶液分馏，以从溶液中除去所有的水; 将溶液冷却至室温; 测定溶液的Pb浓度; 将2-甲氧基乙醇溶液加入到Pb 2-甲氧基乙醇中直到达到所需的Pb浓度; 组合Ge（OR）4，其中R是由CH 2 CH 3和CH（CH 3）2组成的基团和2-甲氧基乙醇; 并向PbO 2 - 甲氧基乙醇中加入Ge（OR）4 2-甲氧基乙醇以形成具有预定的金属离子浓度和预定的Pb:Ge摩尔比的PGO溶液。

公开(公告)号：US06236113B1

公开(公告)日：2001-05-22

申请号：US09263970

申请日：1999-03-05

Applicant: Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC: H01L213205

CPC classification number: H01L28/75 ,  H01L21/28291 ,  H01L28/55 ,  H01L29/516

Abstract: An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

Abstract translation: 已经提供了可用于形成铁电电容器的电极的Ir组合膜。 组合膜包括钽和氧，以及铱。 Ir组合膜有效防止氧气扩散，并且在氧气环境中耐高温退火。 当与下面的Ta或TaN层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 还提供了形成Ir复合膜阻挡层和Ir复合膜铁电电极的方法。

公开(公告)号：US07816753B2

公开(公告)日：2010-10-19

申请号：US12240501

申请日：2008-09-29

Applicant: Fengyan Zhang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Sheng Teng Hsu

IPC: H01L21/00

CPC classification number: C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract translation: 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经接口单晶IrOx纳米结构阵列，其中x＆nlE; 4。 IrOx纳米结构可以部分地涂覆有诸如SiO 2，SiN，TiO 2或旋转玻璃（SOG）之类的电绝缘体，使得IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

公开(公告)号：US07759150B2

公开(公告)日：2010-07-20

申请号：US11805011

申请日：2007-05-22

Applicant: Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Pan ,  Lawrence J. Charneski ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Pan ,  Lawrence J. Charneski ,  Sheng Teng Hsu

IPC: H01L21/00

CPC classification number: G01N27/127 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/41

Abstract: A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over the substrate and intermediate electrode, and a TiO2 film may be formed overlying the TiO2 nanorods. The TiO2 nanorods and TiO2 film are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiO2 film is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiO2 film is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiO2 film from a top noble metal/Pt/Ti multilayered stack overlying the TiO2 film, which has been selectively etched to form separate top electrodes.

Abstract translation: 提供了具有水平对准电极的单个平面的纳米棒传感器和相关联的制造方法。 该方法提供了一个衬底，并形成了覆盖衬底中心区域的中间电极。 中间电极是图案化的底部贵金属/ Pt / Ti多层叠层。 在衬底和中间电极上形成TiO 2纳米棒，并且可以在TiO 2纳米棒上形成TiO 2膜。 通过改变衬底温度，在相同的工艺中原位形成TiO 2纳米棒和TiO 2膜。 在其他方面，在纳米棒和中间电极之间形成TiO 2膜。 在另一方面，在纳米棒上方和下方形成TiO 2膜。 顶层电极的单面由覆盖在TiO 2膜上的顶部贵金属/ Pt / Ti多层叠层覆盖在TiO 2膜上，该TiO 2膜被选择性地蚀刻以形成分离的顶电极。

公开(公告)号：US07635600B2

公开(公告)日：2009-12-22

申请号：US11280423

申请日：2005-11-16

Applicant: Fengyan Zhang ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC: H01L21/00

CPC classification number: H01L51/4213 ,  B82Y10/00 ,  H01L51/0046 ,  H01L51/0048 ,  H01L51/4226 ,  H01L51/4233 ,  H01L51/441 ,  Y02E10/52 ,  Y02E10/549

Abstract: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

Abstract translation: 提供光伏（PV）结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。 该方法包括：形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型（即n型）的第一半导体层; 形成与所述第一掺杂剂类型（即，p型）相反的第二掺杂剂类型的第二半导体层，所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。 第一和第二半导体层可以是诸如导电聚合物，具有富勒烯衍生物的共轭聚合物和诸如CdSe，CdS，二氧化钛或ZnO的无机材料的材料。 导电纳米线可以是诸如IrO 2，In 2 O 3，SnO 2或氧化铟锡（ITO）的材料。

公开(公告)号：US07494840B2

公开(公告)日：2009-02-24

申请号：US11496157

申请日：2006-07-31

Applicant: Fengyan Zhang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Sheng Teng Hsu

IPC: H01L21/00

CPC classification number: C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract translation: 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有电绝缘体，例如SiO 2，SiN，TiO 2或旋转玻璃（SOG），留下IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

公开(公告)号：US20090017197A1

公开(公告)日：2009-01-15

申请号：US11827469

申请日：2007-07-12

Applicant: Fengyan Zhang ,  Ravi K. Reddy ,  Bruce D. Ulrich ,  Shalini Prasad ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Ravi K. Reddy ,  Bruce D. Ulrich ,  Shalini Prasad ,  Sheng Teng Hsu

IPC: B05D5/12 ,  C12M1/00

CPC classification number: G01N33/5438 ,  G01N27/4146

Abstract: An iridium oxide (IrOx) nanowire protein sensor and associated fabrication method are presented. The method provides a substrate and forms overlying working and counter electrodes. A dielectric layer is deposited over the working and counter electrodes and contact holes are formed in the dielectric layer, exposing regions of the working and counter electrodes. IrOx nanowires (where 0≦X≦2) are grown from exposed regions of the working electrode. In one aspect, the IrOx nanowires are additionally grown on the dielectric, and subsequently etched from the dielectric. In another aspect, IrOx nanowires are grown from exposed regions of the counter electrode.

Abstract translation: 提出了一种氧化铱（IrOx）纳米线蛋白传感器及相关制造方法。 该方法提供了一种衬底，并形成了上覆的工作和对电极。 电介质层沉积在工作电极和对电极上，并且在电介质层中形成接触孔，暴露工作电极和对电极的区域。 IrOx纳米线（其中0 <= X <= 2）从工作电极的暴露区域生长。 在一个方面，IrOx纳米线另外在电介质上生长，随后从电介质中蚀刻。 在另一方面，IrOx纳米线从对电极的暴露区域生长。