公开(公告)号：US07723750B2

公开(公告)日：2010-05-25

申请号：US11774221

申请日：2007-07-06

Applicant: Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

Inventor： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

IPC: H01L29/737

CPC classification number: H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

Abstract translation: 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

公开(公告)号：US07709333B2

公开(公告)日：2010-05-04

申请号：US12173098

申请日：2008-07-15

Applicant: Huilong Zhu ,  Oleg Gluschenkov

Inventor： Huilong Zhu ,  Oleg Gluschenkov

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/7624 ,  H01L29/66659 ,  H01L29/7835

Abstract: A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.

Abstract translation: 场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域 仅沿着栅极导体的宽度的选定位置。

公开(公告)号：US07696574B2

公开(公告)日：2010-04-13

申请号：US11163652

申请日：2005-10-26

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L23/62

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207

Abstract: A semiconductor structure and its method for fabrication include a first surface semiconductor layer of a first crystallographic orientation located upon a dielectric surface of a substrate. Located laterally separated upon the dielectric surface from the first surface semiconductor layer is a stack layer. The stack layer includes a buried semiconductor layer located nearer the dielectric surface and a second surface semiconductor layer of a second crystallographic orientation different from the first crystallographic orientation located over and not contacting the buried semiconductor layer. The semiconductor structure provides a pair of semiconductor surface regions of different crystallographic orientation. A particular embodiment may be fabricated utilizing a sequential laminating, patterning, selective stripping and selective epitaxial deposition method.

Abstract translation: 半导体结构及其制造方法包括位于基板的电介质表面上的第一晶体取向的第一表面半导体层。 在第一表面半导体层的电介质表面上横向分离的是堆叠层。 堆叠层包括位于电介质表面附近的掩埋半导体层，以及不同于位于掩埋半导体层之上并且不与埋入半导体层接触的第一晶体取向的第二晶体取向的第二表面半导体层。 半导体结构提供了一对具有不同晶体取向的半导体表面区域。 可以使用顺序层压，图案化，选择性剥离和选择性外延沉积方法来制造特定实施例。

公开(公告)号：US07696040B2

公开(公告)日：2010-04-13

申请号：US11755246

申请日：2007-05-30

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L21/8242

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/10838 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.

Abstract translation: 半导体鳍片存储器结构和半导体鳍片存储器结构的制造方法包括在finFET结构内的半导体鳍片沟道，其与鳍式鳍片FET集成的鳍式电容器结构内的导体鳍状电容器节点相邻并且更薄 结构体。 可以适当地处理单个半导体层以在finFET结构内提供与鳍式电容器结构内的导体鳍状电容器节点相邻并且更薄的半导体鳍状沟道。

公开(公告)号：US07691690B2

公开(公告)日：2010-04-06

申请号：US11622586

申请日：2007-01-12

Applicant: Huilong Zhu ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Zhijiong Luo

IPC: H01L21/00

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Methods for forming fully silicided gates over fins of FinFet devices are disclosed. The disclosure provides methods for patterning a gate stack over each fin from a polysilicon layer and a polysilicon germanium layer, and then removing the polysilicon germanium layer over one of the fins. The disclosure further includes forming a metal layer over both fins and annealing the FinFet device to form fully silicided gates over each fin of the FinFet device.

Abstract translation: 公开了在FinFet装置的翅片上形成完全硅化栅的方法。 本公开提供了用于从多晶硅层和多晶硅锗层在每个鳍上形成栅叠层的方法，然后在一个鳍上去除多晶硅锗层。 本公开还包括在两个翅片上形成金属层并退火FinFet器件以在FinFet器件的每个鳍上形成完全硅化的栅极。

公开(公告)号：US07646039B2

公开(公告)日：2010-01-12

申请号：US11830972

申请日：2007-07-31

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang

IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L29/7843 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/26 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/78654

Abstract: A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated.

Abstract translation: 源极沟槽和漏极沟槽在包括半导体衬底中的第一半导体的顶部半导体层中不对称地形成。 在源极沟槽和漏极沟槽中沉积具有比第一半导体材料窄的带隙的第二半导体材料，以分别形成源极窄带隙区域和漏极侧窄带隙区域。 形成栅极间隔物，并且在顶部半导体层中形成源区和漏极区。 扩展源极区域和延伸体区域之间的边界的一部分形成在源极窄带隙区域中。 由于与第一半导体材料的带隙相比，第二半导体材料的带隙较窄，所以形成在扩展体区域中的电荷通过源放电，并且减少或消除浮体效应。

公开(公告)号：US20090309163A1

公开(公告)日：2009-12-17

申请号：US12136970

申请日：2008-06-11

Applicant: Jing Wang ,  Huilong Zhu

Inventor： Jing Wang ,  Huilong Zhu

IPC: H01L27/092 ,  H01L21/31

CPC classification number: H01L29/7843 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871

Abstract: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack. In an exemplary embodiment, the opening may be extended into an underlying layer such as a source/drain region of the shorter gate stack and a bottom thereof silicided such that a contact formed therein exhibits reduced contact resistance.

Abstract translation: 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。 在示例性实施例中，开口可以延伸到下层，例如较短栅极堆叠的源极/漏极区域，并且其底部被硅化，使得其中形成的接触部显示出降低的接触电阻。

公开(公告)号：US20090256594A1

公开(公告)日：2009-10-15

申请号：US12099989

申请日：2008-04-09

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H03K19/20

CPC classification number: H01H1/0094 ,  H03K19/20 ,  Y10S977/724 ,  Y10S977/742

Abstract: A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S1) and having a first logic signal applied to it, another CNT functioning as second source (S2) and having a second logic signal applied to it, a third CNT functioning as gate (G), and disposed between the two sources (S1, S2). A drain (D) contact is associated with the gate (G). A logic signal applied to the gate (G) causes one or the other of the sources (S1, S2) to deflect, contacting the drain (D) and transferring its logic signal thereto—such as logic “0” on the gate resulting in logic “1” (from one of the sources) being transferred to the drain (D), and logic “1” on the gate resulting in logic “0” (from the other of the sources) being transferred to the drain (D).

Abstract translation: 一种由从基板垂直延伸的三个碳纳米管（CNT）形成的数字逆变器，一个作为第一源（S1）的CNT并且具有施加到其上的第一逻辑信号，另一个CNT用作第二源（S2）并具有第二逻辑 施加到其上的信号，用作门（G）的第三CNT，并且设置在两个源（S1，S2）之间。 漏极（D）触点与栅极（G）相关联。 施加到栅极（G）的逻辑信号使得源（S1，S2）中的一个或另一个偏转，接触漏极（D）并将其逻辑信号传递到门，例如门上的逻辑“0”，导致 逻辑“1”（来自一个源）被传送到漏极（D），并且门上的逻辑“1”导致逻辑“0”（来自另一个源）被传送到漏极（D） 。

公开(公告)号：US20090256205A1

公开(公告)日：2009-10-15

申请号：US12100441

申请日：2008-04-10

Applicant: Qingqing Liang ,  Werner A. Rausch ,  Huilong Zhu

Inventor： Qingqing Liang ,  Werner A. Rausch ,  Huilong Zhu

IPC: H01L29/10 ,  G11C11/34 ,  H01L21/00

CPC classification number: G11C11/412 ,  H01L27/11 ,  Y10S257/903

Abstract: The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.

Abstract translation: 在一个实施例中，本发明提供一种存储器件，其包括包括至少一个器件区域的衬底; 具有第一阈值电压的第一场效应晶体管和具有第二阈值电压的第二场效应晶体管，所述第二场效应晶体管包括存在于所述衬底的所述至少一个器件区域中的第二有源区，所述第二有源区包括 第二漏极和由第二沟道区分隔开的第二源极，其中第二沟道区包括第二陷阱，其存储当第一场效应晶体管处于导通状态时产生的空穴，其中存储在第二陷阱中的空穴增加第二阈值 电压大于第一阈值电压。

公开(公告)号：US20090242941A1

公开(公告)日：2009-10-01

申请号：US12054738

申请日：2008-03-25

Applicant: Huilong Zhu ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823885 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/1037 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

Abstract: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.