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91.发明授权On chip multiple voltage generation using a charge pump and plural feedback sense circuits 失效使用电荷泵和多个反馈感测电路进行片上多电压生成
公开(公告)号：US4752699A
公开(公告)日：1988-06-21
申请号：US943466
申请日：1986-12-19
IPC分类号： H01L21/8247 , G11C5/14 , G11C16/06 , G11C16/30 , G11C17/00 , H01L21/822 , H01L27/04 , H01L29/788 , H01L29/792 , H02M3/00 , H02M3/07 , H03K5/00 , G05F1/571
摘要： A level selectable FET voltage generation system is described. The system includes a single charge pump controlled by multiple feedback paths and a powerdown circuit. Each feedback path contains a capacitor divider network, a sense amplifier with a compensating voltage reference and a timer which periodically resets the capacitor divider network to insure sensing accuracy. The powerdown circuit and a selected feedback path provides a desired voltage level at the output of the charge pump.
摘要翻译： 描述了电平可选FET电压产生系统。 该系统包括由多个反馈路径控制的单个电荷泵和断电电路。 每个反馈路径包含电容分压网络，具有补偿电压基准的读出放大器和周期性地复位电容分压器网络以确保感测精度的定时器。 断电电路和所选择的反馈路径在电荷泵的输出处提供期望的电压电平。
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公开(公告)号：US4404577A
公开(公告)日：1983-09-13
申请号：US164470
申请日：1980-06-30
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02
CPC分类号： G11C16/0433 , H01L29/7883 , H01L29/7885
摘要： A reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate having improved capacitive coupling to the floating gate through a thin oxide grown on single crystal silicon.
摘要翻译： 利用扩散的控制栅极实现单元面积的减小和允许编程和擦除电压的容限的改进，扩散控制栅极通过在单晶硅上生长的薄氧化物具有改善的与浮栅的电容耦合。
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公开(公告)号：US08729908B2
公开(公告)日：2014-05-20
申请号：US13407822
申请日：2012-02-29
IPC分类号： G01R29/26
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/0409 , G11C2029/5002
摘要： A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.
摘要翻译： 一种监视电路和方法，其中具有线性下降沿的电压波形被施加到至少一个测试存储器单元（例如，并联连接的多个测试存储单元）的第一节点。 当在下降沿期间，当测试存储单元的第二个节点处的输出电压上升到高于参考电压时，捕获第一节点处的输入电压。 然后，在捕获的输入电压和（1）第二节点处的输出电压之间确定差异，如在第一节点处的输入电压在下降沿期间低于第一参考电压时捕获的，或者（2） 低参考电压。 该差异与测试存储器单元的静态噪声容限（SNM）成比例，使得通过重复监测指出的差异中的任何变化表示SNM的相应变化。
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94.发明授权Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip 有权用于在非常薄的绝缘体上（ETSOI）集成电路芯片上控制体偏置的解决方案公开(公告)号：US08416009B2
公开(公告)日：2013-04-09
申请号：US13181754
申请日：2011-07-13
IPC分类号： H01L27/12
CPC分类号： G05F1/10 , H01L27/092 , H01L27/1203
摘要： Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
摘要翻译： 公开了用于优化跨越ETSOI设备的衬底的体偏压的解决方案。 在一个实施例中，公开了一种用于优化跨越ETSOI设备的衬底的体偏压的装置，包括：用于感测至少一个预定电路参数的感测电路; 用于向ETSOI装置的基板施加偏置电压的充电电路; 以及连接到所述感测电路和所述充电电路的处理电路，所述处理电路被配置为接收所述感测电路的输出，并且响应于确定所述偏置电压是否偏离所述偏置电压而调整施加到所述ETSOI器件的衬底的偏置电压 目标金额。
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95.发明申请SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP 有权用于控制超薄型绝缘子（ETSOI）集成电路芯片中的块状偏置电压的解决方案公开(公告)号：US20130015911A1
公开(公告)日：2013-01-17
申请号：US13181754
申请日：2011-07-13
CPC分类号： G05F1/10 , H01L27/092 , H01L27/1203
摘要： Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
摘要翻译： 公开了用于优化跨越ETSOI设备的衬底的体偏压的解决方案。 在一个实施例中，公开了一种用于优化跨越ETSOI设备的衬底的体偏压的装置，包括：用于感测至少一个预定电路参数的感测电路; 用于向ETSOI装置的基板施加偏置电压的充电电路; 以及连接到所述感测电路和所述充电电路的处理电路，所述处理电路被配置为接收所述感测电路的输出，并且响应于确定所述偏置电压是否偏离所述偏置电压而调整施加到所述ETSOI器件的衬底的偏置电压 目标金额。
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公开(公告)号：US08219041B2
公开(公告)日：2012-07-10
申请号：US11985963
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
IPC分类号： H04B1/02
CPC分类号： H04L25/0286 , H04L25/03343
摘要： A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. A sensor can be used to detect an operating condition. In response to a change in the detected operating condition, a stored operational parameter corresponding to the detected operating condition can be used to control the frequency response of the transmitter.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构提供具有根据操作参数可控的频率响应的发射机，并且可以包括可操作地存储用于控制每个发射机的频率响应的操作参数的存储器 的多个相应的操作条件。 可以使用传感器来检测操作状态。 响应于检测到的操作条件的变化，可以使用与检测到的操作条件对应的存储的操作参数来控制发送器的频率响应。
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97.发明授权System and method for balancing delay of signal communication paths through well voltage adjustment 有权通过井电压调整来平衡信号通信路径的延迟的系统和方法公开(公告)号：US08051340B2
公开(公告)日：2011-11-01
申请号：US12136359
申请日：2008-06-10
IPC分类号： G01R31/28
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。
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98.发明授权Receiver termination circuit for a high speed direct current (DC) serial link 有权用于高速直流（DC）串行链路的接收器终端电路公开(公告)号：US07995660B2
公开(公告)日：2011-08-09
申请号：US11930975
申请日：2007-10-31
CPC分类号： H04L25/0294 , H04L25/0276
摘要： A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.
摘要翻译： 用于匹配接收机和发射机之间的高速直流（DC）串行连接的接收机和发射机共模电压的方法包括在接收机处测量发射机的共模电压。 发射机的共模电压是发射机发射并由接收机接收的电压信号的平均值。 该方法还包括将发射器的共模电压与接收器的共模电压进行比较。 该方法还包括将接收器的共模电压维持在接收器的共模电压基本上与发射机的共模电压相匹配的第一电平。
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99.发明授权Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path 失效用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构公开(公告)号：US07770139B2
公开(公告)日：2010-08-03
申请号：US11931626
申请日：2007-10-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译： 公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。 特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。 多模电路的工作模式可以动态地选择。 一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。
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公开(公告)号：US07624289B2
公开(公告)日：2009-11-24
申请号：US11949129
申请日：2007-12-03
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
摘要翻译： 提供了一种用于集成电路芯片复合体的网络配电的结构和方法。 芯片复合体具有至少两个扇区，每个扇区具有至少一个功率提供与至少一个所述连接体的连接，所述至少一个所述连接体可以由给定的电源单独寻址并且可与其隔离。 至少一个MEMS被定位成选择性地将所述至少一个连接与所述给定电源连接和断开。
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