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公开(公告)号：US20250048272A1
公开(公告)日：2025-02-06
申请号：US18723066
申请日：2023-02-07
Applicant: INTEL CORPORATION
Inventor： Gang Xiong , Gregory Ermolaev , Dong Han , Bishwarup Mondal , Sergey Sosnin
Abstract: A user equipment (UE) may determine one or more nominal time-domain windows (TDWs) for demodulation reference signals (DMRS) bundling for physical uplink control channel (PUCCH) transmissions of a PUCCH repetition. A start of a new actual TDW for the DMRS bunding is determined in response to an event which causes power consistency and phase continuity not to be maintained across the PUCCH transmissions of the PUCCH repetition. The UE may maintain power consistency and phase continuity within the new actual TDW across two PUCCH transmissions of the PUCCH repetition. The event may comprise a use of different power control parameters for the two of the PUCCH transmissions of the PUCCH repetition within one of the nominal TDWs.
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公开(公告)号：US20250048088A1
公开(公告)日：2025-02-06
申请号：US18924720
申请日：2024-10-23
Applicant: Intel Corporation
Inventor： Abhijeet KOLEKAR
Abstract: This disclosure describes systems, methods, and devices related to sensing authorization. A device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. The device may receive an authorization response from the network based on a UE's subscription status and privacy settings. The device may execute sensing functions locally on the UE upon receiving authorization from the network. The device may transmit sensing data to the network for exposure to authorized clients. The device may update a UE's privacy profile related to sensing data via a communication with a network function.
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公开(公告)号：US20250045219A1
公开(公告)日：2025-02-06
申请号：US18923535
申请日：2024-10-22
Applicant: Intel Corporation
Inventor： Raghavendra RAO , Venkata Mahesh GUNNAM , Eliad Adi KLEIN , David HINES
Abstract: Examples include techniques associated with causing a change to a configuration to access a storage device based on determined bandwidth capabilities for read and write transactions to the storage device and based on a determined needed bandwidth to complete monitored read and write transactions to the storage device. The configuration to be based, at least in part, on coupling to the storage device via a storage interface over a serial bus and the configuration to include a link width for the serial bus, a link speed for the serial bus, or a power state to operate the storage device.
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94.发明申请公开(公告)号：US20250044537A1
公开(公告)日：2025-02-06
申请号：US18362033
申请日：2023-07-31
Applicant: Intel Corporation
Inventor： Chia-Pin Chiu , Kaveh Hosseini
Abstract: A tunable edge-coupled interface for photonic integrated circuits (PICs). The architecture can be identified by (1) an edge interface for optical coupling that exhibits a gap between an oxide cladding layer and the silicon substrate of the PIC die, (2) a perforated beam region above the gap in the oxide layer, wherein waveguide beams in the beam region provide a respective optical path for waveguides of the PIC, (3) actuator beams flanking the waveguide beams, the actuator beams include a heating element and are operated to tune the edge interface by inducing deflection of the edge interface, and (4) an application-specific target pitch of waveguides on the edge interface.
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公开(公告)号：US12219706B2
公开(公告)日：2025-02-04
申请号：US17354989
申请日：2021-06-22
Applicant: Intel Corporation
Inventor： Jonathan W. Thibado , Aaron Gorius , Michael T. Crocker , Matthew J. Adiletta , John C. Gulick , Emery E. Frey
Abstract: Examples described herein relate to an apparatus that includes a flexible conductor covered in an insulative material and at least one conductor region in contact with the flexible conductor. In some examples, melting of the at least one conductor region is to cause a conductive coupling of the flexible conductor with a second conductor and wherein the flexible conductor is adapted to conductively couple a first circuit board oriented orthogonal to a second circuit board. In some examples, the at least one conductor region comprises at least one solder ball of a grid array. In some examples, the at least one conductor region is re-solderable.
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Patent Agency Ranking
公开(公告)号：US12218813B2
公开(公告)日：2025-02-04
申请号：US18215936
申请日：2023-06-29
Applicant: Intel Corporation
Inventor： Marcio Juliato , Javier Perez-Ramirez , Mikhail Galeev , Manoj Sastry , Dave Cavalcanti , Christopher Gutierrez , Shabbir Ahmed , Vuk Lesi
IPC: H04L43/0817 , H04L9/40 , H04L43/067
Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.
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公开(公告)号：US12218408B2
公开(公告)日：2025-02-04
申请号：US17231051
申请日：2021-04-15
Applicant: Intel Corporation
Inventor： Trang Thai , Sidharth Dalmia , Raanan Sover , Josef Hagn , Omer Asaf , Simon Svendsen
Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna board may include: an antenna feed substrate including an antenna feed structure, wherein the antenna feed substrate includes a ground plane, the antenna feed structure includes a first portion perpendicular to the ground plane and a second portion parallel to the ground plane, and the first portion is electrically coupled between the second portion and the first portion; and a millimeter wave antenna patch.
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公开(公告)号：US12218040B2
公开(公告)日：2025-02-04
申请号：US17186289
申请日：2021-02-26
Applicant: Intel Corporation
Inventor： Srinivas V. Pietambaram , Debendra Mallik , Kristof Darmawikarta , Ravindranath V. Mahajan , Rahul N. Manepalli
IPC: H01L23/538 , H01L23/00 , H01L23/498 , H01L25/065
Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.
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公开(公告)号：US12217175B2
公开(公告)日：2025-02-04
申请号：US17560025
申请日：2021-12-22
Applicant: Intel Corporation
Inventor： Rajesh Poornachandran , Vincent Zimmer
IPC: G06F9/46 , G06F9/38 , G06F9/455 , G06F9/48 , G06F9/50 , G06F21/54 , G06N3/042 , G06N3/063 , G06N3/08
Abstract: Methods, apparatus, and articles of manufacture to conditionally activate a big core in a computing system are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request; when the two or more processing devices are available and capable: split the instructions into first sub-instructions and second sub-instructions; provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and generate an output by combining a first output of the first processing device and a second output of the second processing device.
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公开(公告)号：US12217163B2
公开(公告)日：2025-02-04
申请号：US18371934
申请日：2023-09-22
Applicant: Intel Corporation
Inventor： Yiwen Guo , Yuqing Hou , Anbang Yao , Dongqi Cai , Lin Xu , Ping Hu , Shandong Wang , Wenhua Cheng , Yurong Chen , Libin Wang
IPC: G06K9/62 , G06F18/21 , G06F18/213 , G06F18/214 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/08 , G06V10/44 , G06V10/764 , G06V10/82 , G06V10/94 , G06V20/00
Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps. The weighted feature maps are stored in the LSTM. A Q value is calculated for different actions based on the weighted feature maps stored in the LSTM.
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