公开(公告)号：US06643200B2

公开(公告)日：2003-11-04

申请号：US09543131

申请日：2000-04-05

申请人： Lawrence T. Clark ,  Robert D. Bateman

发明人： Lawrence T. Clark ,  Robert D. Bateman

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C7/062

摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a sense amp connected to a plurality of bit lines with bit line transistors. Each of the bit line transistors may be connected to a sense amp enable transistor so that together, the coupling and sense amp enable transistors connect the sense amp to a power supply voltage.

公开(公告)号：US06516384B1

公开(公告)日：2003-02-04

申请号：US09476444

申请日：1999-12-30

申请人： Lawrence T. Clark ,  Matthew M. Clark

发明人： Lawrence T. Clark ,  Matthew M. Clark

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/1027

摘要： A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each register associated with a cache line. The first daisy chain defines a fill order of cache lines and the second daisy chain defines a lock order for the cache lines.

摘要翻译： 第一组多个寄存器与与特定高速缓存线相关联的每个寄存器串联在一起。 类似地，第二多个寄存器与与高速缓存行相关联的每个寄存器串联在一起。 第一个菊花链定义了缓存线的填充顺序，第二个菊花链定义了高速缓存行的锁定顺序。

公开(公告)号：US06487131B1

公开(公告)日：2002-11-26

申请号：US09475491

申请日：1999-12-30

申请人： Lawrence T. Clark ,  Jay B. Miller

发明人： Lawrence T. Clark ,  Jay B. Miller

IPC分类号： G11C700

CPC分类号： G11C15/00 ,  G11C29/12

摘要： In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.

摘要翻译： 在一个实施例中，内容可寻址存储器（CAM）单元的阵列包括第一多个CAM单元和第二多个CAM单元。 第二组多个CAM单元具有足以解决阵列高度的宽度。 第一多个CAM驱动器耦合到阵列以驱动第一多个CAM单元。 当阵列处于测试模式时，第一组多个CAM驱动程序防止第一多个CAM单元参与匹配。

公开(公告)号：US06388475B1

公开(公告)日：2002-05-14

申请号：US09474566

申请日：1999-12-29

申请人： Lawrence T. Clark ,  Adam Brand

发明人： Lawrence T. Clark ,  Adam Brand

IPC分类号： H03B100

CPC分类号： H03K19/00315 ,  H03K17/102

摘要： A series stack including a first and a second MVSD transistor is coupled between a positive power supply and a pad. The series stack has a central node. A p-driver including a first and a second P-type transistor is coupled in series with a source of the first p-type transistor coupled to a positive power supply. The drain of the second p-type transistor is coupled to the central node.

摘要翻译： 包括第一和第二MVSD晶体管的串联堆叠耦合在正电源和焊盘之间。 系列堆栈有一个中心节点。 包括第一和第二P型晶体管的p驱动器与耦合到正电源的第一p型晶体管的源串联耦合。 第二p型晶体管的漏极耦合到中心节点。

公开(公告)号：US06297492B1

公开(公告)日：2001-10-02

申请号：US09003477

申请日：1998-01-06

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： H01J4014

CPC分类号： H01L27/14609 ,  H04N5/3745 ,  H04N5/37452

摘要： A read out circuit is provided. The read out circuit includes an emitter follower circuit (EFC) that receives information indicative of an intensity of light detected by a pixel of an active pixel sensor array. The EFC drives a value related to the information to a read out device when the pixel is accessed.

摘要翻译： 提供读出电路。 读出电路包括射极跟随器电路（EFC），其接收指示由有源像素传感器阵列的像素检测到的光的强度的信息。 当访问像素时，EFC将驱动与读出设备相关的信息值。

公开(公告)号：US6040592A

公开(公告)日：2000-03-21

申请号：US873987

申请日：1997-06-12

申请人： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

发明人： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

IPC分类号： H04N1/028 ,  C07D491/048 ,  H01L27/146 ,  H01L31/10 ,  H01L31/113 ,  H01L31/068 ,  H01L31/0352

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L31/1136

摘要： An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

摘要翻译： 一种具有良好对衬底二极管作为光电检测器的图像传感器。 在优选实施例中，利用现代的水银（CMOS）工艺来制造图像传感器。 二极管结上方的场氧化物区域对于可见光是透明的，因此与在非水银工艺上制造的源/漏扩散至衬底光电二极管的器件相比，光电二极管的竞争量子效率。 光电二极管可以作为具有使用相对未修改的数字CMOS工艺的数字电路的传感器阵列的一部分进行集成。 此外，该结构允许光电二极管的光学性质通过修改阱而不会对其内置于另一相同阱中的FET的特性产生有害影响，即接近于一阶。

公开(公告)号：US5399918A

公开(公告)日：1995-03-21

申请号：US129664

申请日：1993-09-30

申请人： Gregory F. Taylor ,  Lawrence T. Clark

发明人： Gregory F. Taylor ,  Lawrence T. Clark

IPC分类号： G06F15/78 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16

CPC分类号： H03K19/00346 ,  H03K19/09448

摘要： A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

摘要翻译： 高可靠性，大型风扇，高速BiCMOS电路。 通过向基本逻辑电路的每个输入添加双极晶体管的发射极电容，减少了出现在电路的输出线上的MOS晶体管寄生电容的量。 提供电路以提高反向偏置双极晶体管的基极电压，以减少或消除反向偏置。

公开(公告)号：US5272730A

公开(公告)日：1993-12-21

申请号：US811513

申请日：1991-12-20

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： G11B20/10 ,  H03L7/089 ,  H03D3/24

CPC分类号： H03L7/089 ,  G11B20/10212

摘要： A digital filter for a phase-locked loop operates to compare the bit values of the data represented by the incoming pulse stream with patterns in that pulse stream known to produce bit shifting (either early or late). The bit shift caused by physical interaction of bits encoded on computer diskettes or the like always is predictable, in accordance with the pattern of previous bits, the current bit and the next bit. This information is processed by a logic circuit to predict which pulses in the incoming stream of data pulses are shifted. A signal is produced each time a predicted shifted pulse is determined; and this signal is utilized in conjunction with the output of the phase difference counter in the digital phase-locked loop to permit the phase of the controlled oscillator to be adjusted at each unshifted bit in a normal manner, and compensated for adjustment in a modified manner as a result of the prediction of the shifted pulses.

摘要翻译： 用于锁相环的数字滤波器用于将由输入脉冲流表示的数据的比特值与已知产生比特移位（早或晚）的脉冲流中的模式进行比较。 根据先前位的模式，当前位和下一位，总是可以预测由计算机软盘等上编码的位的物理交互引起的位移。 该信息由逻辑电路处理以预测数据脉冲的输入流中的哪些脉冲被移位。 每当确定预测的移位脉冲时产生信号; 并且该信号与数字锁相环中的相位差计数器的输出一起使用，以允许以正常方式在每个未移位位调整受控振荡器的相位，并以修改的方式进行调整 作为移位脉冲的预测的结果。

公开(公告)号：US4897814A

公开(公告)日：1990-01-30

申请号：US202376

申请日：1988-06-06

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： G06F17/30

CPC分类号： G06F17/30982

摘要： A memory system for rapidly choosing a stored item which most closely matches a given input is having a unique memory architecture capable of returning the item stored which most closely correlates to the input. The architecture represents a departure from previous digital content-addressable memories (CAM's) in that it is capable of returning the stored data which most closley resembles the input data rapidly. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates due to pipelining, and is amenable to implementation using conventional digital VLSI fabrication processes.

摘要翻译： 用于快速选择与给定输入最接近匹配的存储项目的存储器系统具有能够返回与输入最密切相关的存储的项目的唯一存储器架构。 该架构代表了与以前的数字内容可寻址存储器（CAM）的偏离，因为它能够快速地返回最接近的输入数据的存储数据。 此外，产生所选（最佳匹配）存储器的质量的量度。 该架构由于流水线而具有显着的数据吞吐率，并且适用于使用常规数字VLSI制造工艺的实现。

公开(公告)号：US09467144B2

公开(公告)日：2016-10-11

申请号：US14808348

申请日：2015-07-24

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： H03K3/00 ,  H03K19/003 ,  H03K19/007

CPC分类号： H03K19/0033 ,  H03K19/0075

摘要： This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.

摘要翻译： 本公开一般涉及辐射硬化的数字电路。 在一个实施例中，辐射硬化的数字电路包括延迟网络和第一Muller C元件。 延迟网络被配置为从全局时钟信号产生第一延迟时钟信号，使得第一延迟时钟信号相对于全局时钟信号被延迟。 第一Muller C元件被配置为产生第一时钟输入信号，并且响应于第一延迟时钟信号和全局时钟信号将第一时钟输入信号设置为一组时钟状态中的一个，每个时钟信号分别以 一组时钟状态，并被配置为保持第一个时钟输入信号。 因此，防止辐射打击在第一时钟输入信号中引起软错误。