公开(公告)号：US07400007B2

公开(公告)日：2008-07-15

申请号：US11305202

申请日：2005-12-19

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi ,  Hirobumi Matsuki ,  Kiyotaka Arai

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi ,  Hirobumi Matsuki ,  Kiyotaka Arai

IPC分类号： H01L27/108

CPC分类号： H01L29/7813 ,  H01L29/0696

摘要： A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.

摘要翻译： 功率MOSFET包括在n型漂移层上分层形成的n型漂移层和p型基极层。 形成沟槽栅极以穿透p型基极层以到达n型漂移层。 在p型基底层上形成n + +型源区和p + + +型区。 这些n + + +型源极区域和p + + +区域沿沟槽栅极的纵向方向交替布置。 相对于沟槽栅极的纵向方向，n + P +型源极区域和p + H +型区域以倾斜的方式排列。

公开(公告)号：US20080099837A1

公开(公告)日：2008-05-01

申请号：US11924175

申请日：2007-10-25

申请人： Miwako AKIYAMA ,  Akio Nakagawa ,  Yusuke Kawaguchi ,  Syotaro Ono ,  Yoshihiro Yamaguchi

发明人： Miwako AKIYAMA ,  Akio Nakagawa ,  Yusuke Kawaguchi ,  Syotaro Ono ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766

摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.

摘要翻译： 该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。 通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。 在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。 第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。

公开(公告)号：US20070272977A1

公开(公告)日：2007-11-29

申请号：US11680912

申请日：2007-03-01

申请人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.

摘要翻译： 功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。 第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

公开(公告)号：US20070262410A1

公开(公告)日：2007-11-15

申请号：US11742133

申请日：2007-04-30

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi ,  Miwako Akiyama

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi ,  Miwako Akiyama

IPC分类号： H01L29/00

CPC分类号： H01L29/872 ,  H01L27/0727 ,  H01L29/66143 ,  H01L29/8725

摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and filling the trench, a first semiconductor region of a second conductivity type provided between the trenches, a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region, a mesa of the semiconductor layer provided between the trenches of a Schottky barrier diode region adjacent to a transistor region including the first semiconductor region and the second semiconductor region, a control electrode connected to the conductive material filling the trench of the transistor region and a main electrode provided in contact with a surface of the first semiconductor region, the second semiconductor region, a surface of the mesa and a part of the conductive material filling the trench of the Schottky barrier diode region. The part is exposed through the insulating film.

摘要翻译： 半导体器件包括：第一导电类型的半导体层，设置在半导体层的主表面侧的多个沟槽，设置在内壁表面上和沟槽顶部上的绝缘膜，由 绝缘膜并填充沟槽，设置在沟槽之间的第二导电类型的第一半导体区域，设置在第一半导体区域的表面部分中的第一导电类型的第二半导体区域，设置在第一半导体区域之间的半导体层的台面 与包括第一半导体区域和第二半导体区域的晶体管区域相邻的肖特基势垒二极管区域的沟槽，连接到填充晶体管区域的沟槽的导电材料的控制电极和与第一半导体区域和第二半导体区域的表面接触的主电极 第一半导体区域，第二半导体区域，台面的表面 以及填充肖特基势垒二极管区域的沟槽的导电材料的一部分。 该部件通过绝缘膜曝光。

公开(公告)号：US20070023793A1

公开(公告)日：2007-02-01

申请号：US11484664

申请日：2006-07-12

申请人： Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Syotaro Ono

发明人： Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Syotaro Ono

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the gate electrode via the gate insulating film; a semiconductor layer having the first conductivity type, being adjacent to the base layer, and facing the gate electrode via the gate insulating film without contacting the source layer; and a contact layer having the second conductivity type, contacting the source layer and base layer, having a top plane continuing with the top plane of the source layer, and having two or more peaks in an impurity concentration value profile in a depth direction from the top plane thereof, the peaks being positioned shallower than a formed depth of the source layer.

摘要翻译： 公开了一种沟槽栅半导体器件，包括：沟槽栅极结构; 具有第一导电类型的源极层，经由栅极绝缘膜面对栅电极，并具有顶面; 具有第二导电类型的基底层，与源极层相邻，并且经由栅极绝缘膜面对栅电极; 具有第一导电类型的半导体层，与基底层相邻，并且经由栅极绝缘膜面对栅电极而不接触源极层; 以及具有第二导电类型的接触层，与源极层和基极层接触，具有与源极层的顶部平面连续的顶面，并且具有两个或更多个沿着深度方向的杂质浓度值分布中的峰 峰位于比源层的形成深度浅的位置。

公开(公告)号：US20060138535A1

公开(公告)日：2006-06-29

申请号：US11362150

申请日：2006-02-27

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/4933

摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

摘要翻译： 垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。 沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。 在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。 基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低 比第一个高峰。 基于第一峰确定阈值电压，并且基于第二峰确定剂量。

公开(公告)号：US07045426B2

公开(公告)日：2006-05-16

申请号：US10826259

申请日：2004-04-19

申请人： Syotaro Ono ,  Yusuke Kawaguchi

发明人： Syotaro Ono ,  Yusuke Kawaguchi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7828

摘要： A power MOSFET comprising a drain layer of a first conductivity type, a drift layer of the first conductivity type provided on the drain layer, a base layer of a first or a second conductivity type provided on the drift layer, a source region of the first conductivity type provided on the base layer, a gate insulating film formed on an inner wall surface of a trench penetrating the base layer and reaching at the drift layer, and a gate electrode provided on the gate insulating film inside the trench, wherein the gate insulating film is formed such that a portion thereof adjacent to the drift layer is thicker than a portion thereof adjacent to the base layer, and the drift layer has an impurity concentration gradient higher in the vicinity of the drain layer and lower in the vicinity of the source region along a depth direction of trench.

摘要翻译： 一种功率MOSFET，包括第一导电类型的漏极层，设置在漏极层上的第一导电类型的漂移层，设置在漂移层上的第一或第二导电类型的基极层，第一导电类型的源极区域 设置在基底层上的导电类型，形成在穿过基底层并到达漂移层的沟槽的内壁表面上的栅极绝缘膜，以及设置在沟槽内部的栅极绝缘膜上的栅电极，其中栅极绝缘 膜形成为使得其与漂移层相邻的部分比与基底层相邻的部分厚，并且漂移层在漏极层附近具有较高的杂质浓度梯度，并且在源极附近较低 区域沿着沟槽的深度方向。

公开(公告)号：US20060081920A1

公开(公告)日：2006-04-20

申请号：US11245204

申请日：2005-10-07

申请人： Kazutoshi Nakamura ,  Syotaro Ono

发明人： Kazutoshi Nakamura ,  Syotaro Ono

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66734

摘要： A semiconductor device includes: a semiconductor substrate of the first-type; a semiconductor region of the first-type formed on the substrate; a gate electrode a part of which is present within a trench selectively formed in part of the semiconductor region, and an extended top-end to have a wide width via a stepped-portion; a gate insulating-film formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second-type on the region via the film to enclose a side-wall except a bottom of the trench; a source region of the first-type adjacent to the film outside the trench in the vicinity of a top surface of the base layer; and an insulating-film formed partially between a bottom-surface of the top-end and a top-surface of the source region and formed to have a thickness larger than that of the gate insulating-film within the trench.

摘要翻译： 半导体器件包括：第一类型的半导体衬底; 在基板上形成第一类型的半导体区域; 栅极电极，其一部分存在于在半导体区域的一部分中选择性地形成的沟槽中，并且延伸的顶端经由阶梯部分具有宽的宽度; 栅沟绝缘膜，沿着沟槽的壁表面形成在沟槽和栅电极之间; 经由膜在该区域上的第二类型的基底层以包围沟槽底部以外的侧壁; 所述第一类型的源极区域在所述基底层的顶表面附近与所述沟槽外部的膜相邻; 以及部分地形成在顶部的底表面和源极区的顶表面之间并且形成为具有比沟槽内的栅极绝缘膜的厚度大的厚度的绝缘膜。

公开(公告)号：US06720618B2

公开(公告)日：2004-04-13

申请号：US10055947

申请日：2002-01-28

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L2976

CPC分类号： H01L21/26513 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41 ,  H01L29/4175 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7835

摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

摘要翻译： 一种功率MOSFET器件，包括第一导电类型的低电阻衬底，形成在低电阻衬底上的第一导电类型的高电阻外延层，形成在高电阻外延表面区域中的第二导电类型的基极层 形成在基底层的表面区域中的第一导电类型的源极区域，形成在基极层的表面上以与源极区域接触的栅极绝缘膜，形成在栅极绝缘膜上的栅电极， 以及形成在所述高电阻外延层的与所述源极区域和所述栅极电极相反的表面上的所述第一导电类型的LDD层，其中所述LDD层和所述低电阻衬底通过所述高电阻外延层彼此连接 。

公开(公告)号：US09093474B2

公开(公告)日：2015-07-28

申请号：US13600616

申请日：2012-08-31

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

摘要翻译： 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。