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    Readout circuit for uncooled infrared focal plane array
    91.
    发明授权
    Readout circuit for uncooled infrared focal plane array 有权

    公开(公告)号：US09163996B2

    公开(公告)日：2015-10-20

    申请号：US14298920

    申请日：2014-06-08

    Applicant: University of Electronic Science and Technology of China

    Inventor： Jian Lv ,  Longcheng Que ,  Yun Zhou ,  Linhai Wei ,  Yadong Jiang

    IPC: G01J5/00 ,  G01J5/10 ,  G01J5/22 ,  G01J5/20

    CPC classification number: G01J5/10 ,  G01J5/20 ,  G01J5/22 ,  G01J2005/106 ,  H04N5/33 ,  H04N5/3651

    Abstract: A readout circuit for an uncooled infrared focal plane array includes: a first biasing circuit for generating a detection output signal; a second biasing circuit for generating a first reference output signal; a first integration circuit; and an analog-to-digital circuit including: a ramp signal generating circuit for generating a ramp signal according to a second reference microbolometer of a third biasing circuit. In the readout circuit, subtracting and amplifying the detection output signal and the first reference output signal are provided by the integrator at an analog domain, while ratio counting is provided by an analog-to-digital converter during analog-to-digital conversion. Furthermore, a column level integrated readout channel utilizes only one reference microbolometer, and the chip level ramp signal generator also utilizes only one reference microbolometer. Therefore, a chip area is further saved, and noise sources are decreased.

    ULTRA LOW-POWER PIPELINED PROCESSOR
    92.
    发明申请
    ULTRA LOW-POWER PIPELINED PROCESSOR 有权
    超低功率流水线加工机

    公开(公告)号：US20140304572A1

    公开(公告)日：2014-10-09

    申请号：US13929758

    申请日：2013-06-27

    Applicant: University of Electronic Science and Technology of China

    Inventor： Yajuan HE ,  Tingting XIA ,  Tao LUO ,  Wubing GAN ,  Bo ZHANG

    IPC: G06F11/25

    CPC classification number: G01R31/317 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/152 ,  Y02D10/172

    Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

    Abstract translation: 一种流水线处理器，包括几级的组合逻辑，电压调节器，计数器，比较器和多个级寄存器。 每个级寄存器被布置在组合逻辑的两个相邻级之间。 级寄存器包括触发器，锁存器，异或门和MUX模块。 当寄存器时钟的高电平到来时，触发器在上升沿锁存第一数据，并且锁存器在高电平期间接收第二数据。 由触发器和锁存器锁存的数据分别由XOR门进行比较。 如果它们相同，则XOR门的输出误差为低电平，触发器的输出被传送到下一级。 否则，异或门的输出误差为高电平，并将锁存器的输出传送到下一级。

    Multi-level gate driver applied to SiC MOSFET
    95.
    发明授权
    Multi-level gate driver applied to SiC MOSFET 有权

    公开(公告)号：US12199150B2

    公开(公告)日：2025-01-14

    申请号：US17848422

    申请日：2022-06-24

    Applicant: University of Electronic Science and Technology of China

    Inventor： Zekun Zhou ,  Jianwen Cao ,  Yue Shi ,  Bo Zhang

    IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

    Scattering aperture imaging method and device, system, and storage medium
    96.
    发明授权
    Scattering aperture imaging method and device, system, and storage medium 有权

    公开(公告)号：US12181572B1

    公开(公告)日：2024-12-31

    申请号：US18652208

    申请日：2024-05-01

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

    Inventor： Jiang Qian ,  Jiayang Wu ,  Haitao Lyu ,  Guangcai Sun

    IPC: G01S13/90 ,  G01S7/295

    Abstract: Provided are a scattering aperture imaging method and a device, a system and a storage medium. The method mainly includes four steps of scattering point position estimation, azimuth resampling, range compensation and synthetic aperture radar imaging. A phased array radar with a fixed position is used for NLOS imaging, and the radar can control a beam to scan in space, which is equivalent to a scattering aperture moving along a relay surface. Therefore, the method can realize converting NLOS imaging into LOS synthetic aperture radar imaging, which can be suitable for the situation that a relay surface is rough and the relay surface with more complicated surface condition, thus widening the application range of radar NLOS imaging.

    LATERAL POWER SEMICONDUCTOR DEVICE
    97.
    发明申请
    LATERAL POWER SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240395930A1

    公开(公告)日：2024-11-28

    申请号：US18382561

    申请日：2023-10-23

    Applicant: University of Electronic Science and Technology of China

    Inventor： Ming QIAO ,  Yue GAO ,  Jiawei WANG ,  Dingxiang MA ,  Bo ZHANG

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

    Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

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