公开(公告)号：US08987049B2

公开(公告)日：2015-03-24

申请号：US14474433

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。

公开(公告)号：US20150053935A1

公开(公告)日：2015-02-26

申请号：US14229232

申请日：2014-03-28

Applicant: Apple Inc.

Inventor： Vasudha Gupta ,  Jae Won Choi ,  Shih Chang Chang ,  Tsung-Ting Tsai ,  Young Bae Park

IPC: H01L27/32 ,  H01L27/12

CPC classification number: H01L27/3262 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  G09G3/3225 ,  G09G3/3611 ,  G09G3/3677 ,  G09G2320/043 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract translation: 电子设备可以包括在基板上具有显示像素阵列的显示器。 显示像素可以是液晶显示器中的有机发光二极管显示像素或显示像素。 在有机发光二极管显示器中，可以形成包括半导体氧化物薄膜晶体管，硅薄膜晶体管和电容器结构的混合薄膜晶体管结构。 电容器结构可以与半导体氧化物薄膜晶体管重叠。 有机发光二极管显示像素可以具有氧化物和硅晶体管的组合。 在液晶显示器中，显示驱动器电路可以包括硅薄膜晶体管电路，显示像素可以基于氧化物薄膜晶体管。 可以在形成硅晶体管栅极和氧化物晶体管栅极中使用单层或两层不同的栅极金属层。 硅晶体管可以具有与浮动栅极结构重叠的栅极。

公开(公告)号：US20140141565A1

公开(公告)日：2014-05-22

申请号：US13679767

申请日：2012-11-16

Applicant: APPLE INC.

Inventor： Ming-Chin Hung ,  Young Bae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: Embodiments of the present disclosure relate to display devices and methods for manufacturing display devices. Specifically, embodiments of the present disclosure employ an enhanced etching process to create uniformity in the gate insulator of thin-film-transistor (TFTs) by using an active layer to protect the gate insulator from inadvertent etching while patterning an etch stop layer.

Abstract translation: 本公开的实施例涉及用于制造显示设备的显示设备和方法。 具体地，本公开的实施例采用增强的蚀刻工艺，以通过使用有源层来在薄膜晶体管（TFT）的栅极绝缘体中产生均匀性，以保护栅极绝缘体免受无意蚀刻，同时图案化蚀刻停止层。

公开(公告)号：US20140070225A1

公开(公告)日：2014-03-13

申请号：US14020620

申请日：2013-09-06

Applicant: Apple Inc.

Inventor： Cheng-Ho Yu ,  Marduke Yousefpor ,  Yu-Cheng Chen ,  Stephen S. Poon ,  Ting-Kuo Chang ,  Young Bae Park

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78675 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66757

Abstract: A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer Cgd upon a bias voltage being applied between the gate metal electrode and the conductive layer.

Abstract translation: 提供了一种用于液晶显示器的TFT堆叠。 TFT堆叠包括硅层，其包括重掺杂区域，非掺杂区域和重掺杂区域和非掺杂区域之间的轻掺杂区域。 重掺杂区被氢化。 TFT堆叠还包括绝缘层，其包括形成在轻掺杂区域上的第一部分和设置在非掺杂区域上的第二部分，以及形成在非掺杂区域的第二部分上的栅极金属电极层。 TFT堆叠还包括设置在栅极金属电极上方并在绝缘层的第一部分之上的第一介电层。 氢化重掺杂区域，以便在施加在栅极金属电极和导电层之间的偏置电压时，减小栅极金属电极和导电层Cgd之间的电容的依赖性。

公开(公告)号：US20140042427A1

公开(公告)日：2014-02-13

申请号：US13629537

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。

公开(公告)号：US20130235003A1

公开(公告)日：2013-09-12

申请号：US13661839

申请日：2012-10-26

Applicant: APPLE INC.

Inventor： Shih Chang Chang ,  Young Bae Park ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Szu-Hsien Lee

IPC: G06F3/038

CPC classification number: G09G3/3677

Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.

Abstract translation: 栅极线驱动器电路将输出脉冲施加到用于显示元件阵列的多个栅极线中的每一个。 电路具有多个栅极驱动器，每个栅极驱动器被耦合以驱动相应的一条栅极线。 每个栅极驱动器具有输出级，其中高侧晶体管和低侧晶体管耦合以响应于至少一个时钟信号驱动相应的栅极线。 耦合下拉晶体管以放电输出级的控制电极。 具有共源共栅放大器的控制电路被耦合以作为a）至少一个时钟信号和b）来自控制电极的反馈来驱动下拉晶体管。 还描述和要求保护其他实施例。

公开(公告)号：US20130147774A1

公开(公告)日：2013-06-13

申请号：US13762276

申请日：2013-02-07

Applicant: Apple Inc.

Inventor： Cheng Ho Yu ,  Ming Xu ,  Young Bae Park ,  Zhibing Ge ,  Daisuke Nozu ,  Cheng Chen ,  Abbas Jamshidi Roudbari ,  Shih Chang Chang ,  Shawn R. Gettemy

IPC: G09G3/18

CPC classification number: G09G3/18 ,  G02F1/13338 ,  G02F2001/134318 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/043 ,  G09G2310/0224 ,  G09G2310/0283 ,  G09G2320/0209

Abstract: Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.

Abstract translation: 显示接地平面结构可能包含狭缝。 显示器中的图像像素电极可以以行和列布置。 可以使用与与列相关联的行和数据行相关联的门线来控制显示器中的图像像素。 可以通过延伸穿过液晶层的每个图像像素电极产生电场到接地平面的相关部分。 接地平面中的狭缝可以具有狭缝宽度。 数据线可以充分地位于接地平面的下方，并且与狭缝充分地不对齐，以使来自寄生电场的串扰最小化。 当将数据线信号驱动到显示器中时，可以使用三列反转方案，使得跨越狭缝的像素对各自以共同的极性驱动。 可以使用增强显示均匀性的栅极线扫描图案。