公开(公告)号：US20050263831A1

公开(公告)日：2005-12-01

申请号：US11122193

申请日：2005-05-04

申请人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

发明人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L31/113

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

公开(公告)号：US06916698B2

公开(公告)日：2005-07-12

申请号：US10795672

申请日：2004-03-08

申请人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

发明人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

摘要翻译： 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

公开(公告)号：US20050127408A1

公开(公告)日：2005-06-16

申请号：US10735736

申请日：2003-12-16

申请人： Bruce Doris ,  Meikei Ieong ,  Thomas Kanarsky

发明人： Bruce Doris ,  Meikei Ieong ,  Thomas Kanarsky

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/1203 ,  H01L21/823814 ,  H01L21/84

摘要： Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.

摘要翻译： 薄硅沟道SOI器件具有更清晰的子阈值斜率，高迁移率和更好的短沟道效应控制的优点，但呈现增加串联电阻的典型缺点。 通过使用升高的源极 - 漏极（RSD）和使用在nFET和pFET之间去耦合的选择性外延Si生长来扩展CMOS对中的pFET晶体管上的源极漏极来避免该高串联电阻。 通过这样做，串联电阻得到改善，扩展在RSD形成后植入，因此不暴露于RSD工艺的高热预算，而pFET和nFET可以实现独立的有效偏移。

公开(公告)号：US20050093104A1

公开(公告)日：2005-05-05

申请号：US10696634

申请日：2003-10-29

申请人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

发明人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L29/04

CPC分类号： H01L21/823878 ,  H01L21/76254 ,  H01L21/823807

摘要： A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.

摘要翻译： 提供半导体到半导体直接晶片接合以提供具有由导电界面分离的不同晶体取向的半导体层的混合基板的方法。 还提供了通过该方法制造的混合基板以及使用直接接合方法来提供其中各种CMOS器件构建在增强器件性能的表面取向上的集成半导体结构。

公开(公告)号：US20050093077A1

公开(公告)日：2005-05-05

申请号：US10799380

申请日：2004-03-12

申请人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

发明人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823878 ,  H01L21/76254 ,  H01L21/823807

摘要： A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive or insulating interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.

摘要翻译： 提供半导体到半导体直接晶片接合以提供具有由导电或绝缘界面分隔的不同晶体取向的半导体层的混合基板的方法。 还提供了通过该方法制造的混合基板以及使用直接接合方法来提供其中各种CMOS器件构建在增强器件性能的表面取向上的集成半导体结构。

公开(公告)号：US20050048752A1

公开(公告)日：2005-03-03

申请号：US10650229

申请日：2003-08-28

申请人： Bruce Doris ,  Thomas Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

发明人： Bruce Doris ,  Thomas Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/3205

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/78612 ,  H01L29/78621

摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

摘要翻译： 描述了制造薄沟道硅绝缘体上结构的方法。 本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域 ，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

公开(公告)号：US20050003589A1

公开(公告)日：2005-01-06

申请号：US10862073

申请日：2004-06-04

申请人： Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Wesley Natzle

发明人： Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Wesley Natzle

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L31/0392

CPC分类号： H01L21/84 ,  H01L21/76283

摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

公开(公告)号：US06821826B1

公开(公告)日：2004-11-23

申请号：US10674644

申请日：2003-09-30

申请人： Victor Chan ,  Kathryn W. Guarini ,  Meikei Ieong

发明人： Victor Chan ,  Kathryn W. Guarini ,  Meikei Ieong

IPC分类号： H01L2904

CPC分类号： H01L21/6835 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

摘要翻译： 提供制造3D集成电路的三维（3D）积分方案，其中pFET位于该器件的最佳晶体表面上，并且nFET位于用于该类型器件的最佳晶体表面上。 根据本发明的第一3D集成方案，第一半导体器件预先构建在第一绝缘体上硅（SOI）衬底的半导体表面上，并且第二半导体器件预先构建在第一绝缘体上硅绝缘体 第二SOI衬底。 在预先构建这两个结构之后，将结构粘合在一起并通过晶片通孔通孔进行互连。 在第二3D集成方案中，具有第一晶体取向的第一SOI层的绝缘硅绝缘体（SOI）衬底被结合到具有第二SOI层的具有第二半导体器件的预制晶片的表面上，所述第二SOI层具有 不同于第一SOI层的晶体取向; 以及在所述第一SOI层上形成第一半导体器件。

公开(公告)号：US08785281B2

公开(公告)日：2014-07-22

申请号：US13369707

申请日：2012-02-09

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US07943486B2

公开(公告)日：2011-05-17

申请号：US12115731

申请日：2008-05-06

申请人： Victor Chan ,  Massimo V. Fischetti ,  John M. Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul M. Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo V. Fischetti ,  John M. Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul M. Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/30

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

摘要翻译： 本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。 本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。 本发明的另一方面涉及形成本发明的半导体材料的方法。 本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。