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17 条记录 (耗时 0.031 秒)

    Hybrid planar and FinFET CMOS devices
    1.
    发明申请
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US20050263831A1

    公开(公告)日：2005-12-01

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

    发明人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

    IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L31/113

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    Sectional field effect devices and method of fabrication
    2.
    发明申请
    Sectional field effect devices and method of fabrication 有权
    截面场效应器件及其制造方法

    公开(公告)号：US20050127362A1

    公开(公告)日：2005-06-16

    申请号：US10732322

    申请日：2003-12-10

    申请人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Jakub Kedzierski

    发明人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Jakub Kedzierski

    IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

    摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。

    Sectional field effect devices and method of fabrication
    4.
    发明申请
    Sectional field effect devices and method of fabrication 有权
    截面场效应器件及其制造方法

    公开(公告)号：US20060240607A1

    公开(公告)日：2006-10-26

    申请号：US11433806

    申请日：2006-05-13

    申请人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Jeong ,  Jakub Kedzierski

    发明人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Jeong ,  Jakub Kedzierski

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

    摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。

    METHOD AND APPARATUS FOR FABRICATING CMOS FIELD EFFECT TRANSISTORS
    5.
    发明申请
    METHOD AND APPARATUS FOR FABRICATING CMOS FIELD EFFECT TRANSISTORS 审中-公开
    制造CMOS场效应晶体管的方法和装置

    公开(公告)号：US20070128785A1

    公开(公告)日：2007-06-07

    申请号：US11671113

    申请日：2007-02-05

    申请人： CYRIL CABRAL ,  Meikei Ieong ,  Jakub Kedzierski

    发明人： CYRIL CABRAL ,  Meikei Ieong ,  Jakub Kedzierski

    IPC分类号： H01L21/8238 ,  H01L27/10

    CPC分类号： H01L29/66628 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835

    摘要： A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

    摘要翻译： 制造互补金属氧化物半导体（CMOS）场效应晶体管的方法，其包括选择性掺杂和包括晶体管的栅电极的多晶硅材料的全硅化。 在一个实施方案中，在硅化之前，多晶硅是非晶化的。 在另一个实施方案中，在低的衬底温度下进行硅化。

    Ultrathin-body schottky contact MOSFET
    7.
    发明申请
    Ultrathin-body schottky contact MOSFET 审中-公开
    超薄体肖特基接触MOSFET

    公开(公告)号：US20070001223A1

    公开(公告)日：2007-01-04

    申请号：US11172711

    申请日：2005-07-01

    申请人： Diane Boyd ,  Meikei Leong ,  Jakub Kedzierski ,  Ghavam Shahidi

    发明人： Diane Boyd ,  Meikei Leong ,  Jakub Kedzierski ,  Ghavam Shahidi

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66643 ,  H01L29/66772 ,  H01L29/78654

    摘要： An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.

    摘要翻译： 提出了一种超薄SOI MOSFET器件结构及其制造方法。 该器件具有由硅化物构成的端子，该端子与沟道形成肖特基接触。 多个杂质在硅化物/沟道界面上分离，这些分离的杂质决定了肖特基接触的电阻。 这种杂质偏析通过所谓的硅化物诱导的杂质分离过程来实现。 硅替代杂质适合于实现这种分离。

    METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION
    10.
    发明申请
    METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION 审中-公开
    金属栅MOSFET通过全半导体金属合金转换

    公开(公告)号：US20070034967A1

    公开(公告)日：2007-02-15

    申请号：US11537718

    申请日：2006-10-02

    申请人： Hasan Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub Kedzierski ,  Cyril Cabral

    发明人： Hasan Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub Kedzierski ,  Cyril Cabral

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.

    摘要翻译： 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换为半导体金属合金 MOSFET类型区域。 在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。