摘要:
Method, system and article of manufacture are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.
摘要:
A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要:
Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要:
An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.
摘要:
Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要:
Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要:
One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要:
A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.
摘要:
An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops.
摘要:
One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.