公开(公告)号：US20070075377A1

公开(公告)日：2007-04-05

申请号：US11243959

申请日：2005-10-05

申请人： Chien-Chao Huang ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L29/76

CPC分类号： H01L21/823412 ,  H01L21/823481 ,  H01L29/1037

摘要： A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with a tilt angle of substantially less than 90 degrees. The active region is recessed. By recessing the active region, the channel width is increased and device drive current is improved.

摘要翻译： 提供具有凹入的有源区的半导体结构及其形成方法。 半导体结构包括在其间具有有源区的第一和第二隔离结构。 第一和第二隔离结构具有基本上小于90度的倾斜角的侧壁。 活动区域是凹进的。 通过使有源区域凹陷，通道宽度增加并且器件驱动电流得到改善。

公开(公告)号：US20070023755A1

公开(公告)日：2007-02-01

申请号：US11190992

申请日：2005-07-27

申请人： Chien-Chao Huang ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L29/04

CPC分类号： H05B33/10

摘要： A semiconductor light emitting device and a method to form the same are disclosed. The device has at least one porous or low density dielectric region formed in or on top of a bottom electrode, at least one top electrode on the porous or low density dielectric region, and one or more color filters placed above the top electrode, wherein the porous or low density dielectric region contains light emitting nanocrystal materials.

摘要翻译： 公开了一种半导体发光器件及其形成方法。 该器件具有至少一个多孔或低密度电介质区域，形成在底部电极中的顶部或顶部上，多孔或低密度电介质区域上的至少一个顶部电极以及置于顶部电极上方的一个或多个滤色器，其中， 多孔或低密度电介质区域包含发光纳米晶体材料。

公开(公告)号：US20070012905A1

公开(公告)日：2007-01-18

申请号：US11180430

申请日：2005-07-13

申请人： Chien-Chao Huang

发明人： Chien-Chao Huang

IPC分类号： H01L29/02

CPC分类号： H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective coating (ARC) film on the bottom electrode film, patterning and etching the ARC film and the bottom electrode film to form a bottom electrode comprising a side edge, and forming a phase change material portion on the ARC film and the bottom insulating layer, wherein the phase change material portion physically contacts the side edge of the bottom electrode. The method further includes forming a top electrode on the phase change material portion, and forming a top electrode contact on the top electrode.

摘要翻译： 提供了具有减小的相变容积和较低驱动电流的相变存储器件及其形成方法。 该方法包括形成底部绝缘层，该底部绝缘层包括底部电极触点，在底部电极触点上形成底部电极膜，在底部电极膜上形成抗反射涂层（ARC）膜，对ARC膜和底部 形成包括侧边缘的底部电极，并且在所述ARC膜和所述底部绝缘层上形成相变材料部分，其中所述相变材料部分物理接触所述底部电极的侧边缘。 该方法还包括在相变材料部分上形成顶部电极，以及在顶部电极上形成顶部电极接触。

公开(公告)号：US20060237770A1

公开(公告)日：2006-10-26

申请号：US11111282

申请日：2005-04-20

申请人： Chien-Chao Huang ,  Chi Min-Hwa ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Chi Min-Hwa ,  Fu-Liang Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L29/42324

摘要： A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.

公开(公告)号：US07053453B2

公开(公告)日：2006-05-30

申请号：US10863600

申请日：2004-06-08

申请人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L29/76

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.

摘要翻译： 基板接触和半导体芯片及其形成方法。 基板接触可以由半导体基板形成的半导体芯片使用，并且包括围绕集成电路区域的周边的密封环区域。 在一个实施例中，衬底接触包括延伸穿过浅沟槽隔离区域的接触沟槽和覆盖在半导体衬底上以及集成电路区域之外的绝缘体。 接触沟槽基本上填充有导电材料，从而允许半导体衬底与密封环区域内的金属互连电连接。

公开(公告)号：US20060110887A1

公开(公告)日：2006-05-25

申请号：US10994841

申请日：2004-11-22

申请人： Chien-Chao Huang

发明人： Chien-Chao Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659

摘要： Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of the semiconductor substrate layer. A semiconductor layer is then formed in the openings directly upon the exposed portions of the semiconductor substrate layer using a second material different from the first material (e.g., silicon germanium or silicon). In other examples, multiple semiconductor layers may be formed using alternating materials.

公开(公告)号：US20060102964A1

公开(公告)日：2006-05-18

申请号：US11112655

申请日：2005-04-22

申请人： Chien-Chao Huang

发明人： Chien-Chao Huang

IPC分类号： H01L29/76

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0688

摘要： An integrated circuit includes an active device, having a metal gate electrode, disposed on a substrate. A passive device, made of a semiconductor material, is disposed adjacent to the active device above the substrate. A dielectric layer is interposed between the passive device and the substrate for separating the same.

公开(公告)号：US20060051922A1

公开(公告)日：2006-03-09

申请号：US10937722

申请日：2004-09-09

申请人： Chien-Chao Huang ,  Cheng-Chuan Huang ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Cheng-Chuan Huang ,  Fu-Liang Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/78621

摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

摘要翻译： 微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。 邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。 在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。 在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。 然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

公开(公告)号：US20050236712A1

公开(公告)日：2005-10-27

申请号：US10863600

申请日：2004-06-08

申请人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L23/00 ,  H01L23/52 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.

摘要翻译： 基板接触和半导体芯片及其形成方法。 基板接触可以由半导体基板形成的半导体芯片使用，并且包括围绕集成电路区域的周边的密封环区域。 在一个实施例中，衬底接触包括延伸穿过浅沟槽隔离区域的接触沟槽和覆盖在半导体衬底上以及集成电路区域之外的绝缘体。 接触沟槽基本上填充有导电材料，从而允许半导体衬底与密封环区域内的金属互连电连接。

公开(公告)号：US20050230763A1

公开(公告)日：2005-10-20

申请号：US10824854

申请日：2004-04-15

申请人： Chien-Chao Huang ,  Cheng-Kuo Wen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Cheng-Kuo Wen ,  Fu-Liang Yang

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823842 ,  H01L29/41791 ,  H01L29/7833 ,  H01L2029/7858

摘要： A method of manufacturing a microelectronic device. The method includes providing a substrate and forming a patterned feature located over the substrate and a plurality of doped regions. The patterned feature also comprises at least one electrode, wherein the electrode is proximate a plurality of doped layers. The method further includes forming a sill located within the electrode, wherein the sill comprising at least one impurity and adapted for modifying an electrical property of at least one member adjacent the electrode.

摘要翻译： 一种制造微电子器件的方法。 该方法包括提供衬底并形成位于衬底上方的图案化特征以及多个掺杂区域。 图案化特征还包括至少一个电极，其中电极接近多个掺杂层。 所述方法还包括形成位于所述电极内的基台，其中所述基底包括至少一种杂质并且适于改变邻近所述电极的至少一个构件的电性能。