公开(公告)号：US06265259B1

公开(公告)日：2001-07-24

申请号：US09351876

申请日：1999-07-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218238

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/518

Abstract: The method of the present invention is to fabricate a CMOS device without boron penetration. Firstly, a gate oxide layer is formed on a semiconductor substrate. A first silicon layer is formed upon the gate oxide layer. Thereafter, a second silicon layer is stacked on the first silicon substrate, and N type dopant is in situ doped into the second silicon layer, and then a third silicon layer is stacked upon the second silicon layer. A gate structure is formed by patterning the stacked silicon layers, and source/drain structures with LDD regions are subsequently formed in the substrate by ion implantation processes. Finally, a thermal treatment is performed to form shallow source and drain junction in the substrate, thereby achieving the structure of the CMOS device. Meanwhile, the N type dopant is driven to the boundaries of stacked silicon layers of gate structure so as to act as diffusion barriers for suppressing boron penetration.

Abstract translation: 本发明的方法是制造没有硼渗透的CMOS器件。 首先，在半导体基板上形成栅氧化层。 在栅氧化层上形成第一硅层。 此后，在第一硅衬底上堆叠第二硅层，并且将N型掺杂剂原位掺杂到第二硅层中，然后在第二硅层上层叠第三硅层。 通过图案化层叠的硅层形成栅极结构，随后通过离子注入工艺在衬底中形成具有LDD区的源极/漏极结构。 最后，进行热处理以在衬底中形成浅源极和漏极结，从而实现CMOS器件的结构。 同时，N型掺杂剂被驱动到栅极结构的层叠硅层的边界，以便作为用于抑制硼渗透的扩散阻挡层。

公开(公告)号：US06207526B1

公开(公告)日：2001-03-27

申请号：US09353508

申请日：1999-07-14

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218242

CPC classification number: H01L28/82 ,  H01L28/87 ,  H01L28/91

Abstract: The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is then formed over the nitride layer and a first silicon layer is formed over the second oxide layer. Next, a node opening is defined in the first silicon layer, the second oxide layer, and the nitride layer, upon the first oxide layer. Sidewall structures are then formed on sidewalls of the node opening. A contact opening is then defined in the first oxide layer under the node opening. The contact opening is defined in the first oxide layer under a region uncovered by the sidewall structures. The sidewall structures and a portion of the nitride layer nearby the node opening are removed to form undercut structures under the second oxide layer. A second silicon layer is then formed conformably over the contact opening, the undercut structures, the node opening, and the first silicon layer. A node-top defining layer is formed on the second silicon layer and is patterned to leave a node-top defining region. Next, a portion of the second silicon layer and a portion of the first silicon layer uncovered by the node-top defining region are removed. Silicon sidewalls are formed on sidewalls of the node-top defining region, and are communicated to the first silicon layer and the second silicon layer to form an electrode. The node-top defining region, the second oxide layer, and the nitride layer are removed. A wet etch is performed to remove the nitride layer and to roughen the surface of the electrode. A dielectric film is then formed conformably over the electrode. Finally, a conductive layer is formed over the dielectric layer.

Abstract translation: 本发明的用于在半导体衬底上形成电容器的方法包括以下步骤。 首先，在衬底上形成第一氧化物层，然后在氧化物层上形成氮化物层。 然后在氮化物层上形成第二氧化物层，并且在第二氧化物层上形成第一硅层。 接下来，在第一氧化物层上，在第一硅层，第二氧化物层和氮化物层中限定节点开口。 然后在节点开口的侧壁上形成侧壁结构。 然后在节点开口下方的第一氧化物层中限定接触开口。 接触开口限定在第一氧化物层的未被侧壁结构覆盖的区域之下。 去除侧壁结构和在节点开口附近的氮化物层的一部分，以在第二氧化物层下形成底切结构。 然后在接触开口，底切结构，节点开口和第一硅层上顺应地形成第二硅层。 节点顶部限定层形成在第二硅层上并被图案化以留下节点顶部限定区域。 接下来，去除第二硅层的一部分和未被节点顶部限定区域覆盖的第一硅层的一部分。 硅侧壁形成在节点顶部限定区域的侧壁上，并且与第一硅层和第二硅层连通以形成电极。 去除节点顶部限定区域，第二氧化物层和氮化物层。 执行湿蚀刻以去除氮化物层并使电极的表面变粗糙。 然后在电极上顺应地形成电介质膜。 最后，在电介质层上形成导电层。

公开(公告)号：US6156591A

公开(公告)日：2000-12-05

申请号：US8157

申请日：1998-01-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238 ,  H01L2/8238

CPC classification number: H01L21/823892

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an n-well region is defined by implanting a high energy dose phosphorous in the semiconductor substrate. When the photoresist layer used for defining the n-well is stripped, a high energy and low dose blanket boron is implanted under the n-well region in the semiconductor substrate. Next, both the silicon nitride layer and the pad oxide layer are removed. A high temperature steam oxidation process is then performed to remove the crystalline defects, and the in-situ high temperature long time anneal is done to form a deep twin-well. A thick pad oxide layer formed by the high temperature steam oxidation is then removed, and an active region is defined followed by a standard oxidation process to grow a thick field oxide region. After a phosphorous punch-through stopping implant is performed in the semiconductor substrate for the PMOSFET, another high energy and low dose blanket boron is implanted in a semiconductor substrate for increasing the threshold voltage of the NMOSFET field oxide device. Both the threshold voltages of the buried channel PMOSFET and surface channel NMOSFET are then adjusted by a low energy and low dose blanket BF.sub.2 implant. Finally, the standard processes can be employed for fabricating the CMOS transistors.

Abstract translation: 本发明公开了一种通过使用更少的掩模计数来形成具有自对准平面化双阱的CMOS晶体管的方法。 在半导体衬底上的衬垫氧化物层之上形成氮化硅层之后，通过在半导体衬底中注入高能量剂量磷来限定n阱区。 当用于限定n阱的光致抗蚀剂层被剥离时，在半导体衬底中的n阱区域下方注入高能量和低剂量覆盖层硼。 接下来，去除氮化硅层和衬垫氧化物层。 然后进行高温蒸汽氧化处理以除去晶体缺陷，并且进行原位高温长时间退火以形成深双阱。 然后去除通过高温蒸汽氧化形成的厚焊盘氧化物层，并且定义有源区，随后进行标准氧化工艺以生长厚的氧化物区域。 在用于PMOSFET的半导体衬底中执行磷穿通停止注入之后，将另一高能量和低剂量覆盖层硼注入到半导体衬底中以增加NMOSFET场氧化物器件的阈值电压。 掩埋沟道PMOSFET和表面沟道NMOSFET的阈值电压随后通过低能量和低剂量层BF2植入来调节。 最后，可以采用标准工艺来制造CMOS晶体管。

公开(公告)号：US6137152A

公开(公告)日：2000-10-24

申请号：US64976

申请日：1998-04-22

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/762 ,  H01L29/00

CPC classification number: H01L21/76227 ,  H01L21/76232

Abstract: The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.

Abstract translation: 本发明的沟槽隔离结构如下。 下半部沟槽在衬​​底中。 衬底中的上半沟槽位于下半沟槽上方，并且上半沟槽具有比下半沟槽更大的宽度。 第一绝缘层位于下半沟槽和上半沟槽的正上方。 第二绝缘层位于第一绝缘层上。 半导体层在第二绝缘层的一部分上方的下半沟槽内。 第三绝缘层位于第二绝缘层和半导体层上，位于上半沟槽内。 本发明中的平面化深浅沟槽隔离可用于隔离CMOS和双极器件。 提供比常规沟槽隔离更高的堆积密度。

公开(公告)号：US6136636A

公开(公告)日：2000-10-24

申请号：US291265

申请日：1999-04-14

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/28052 ,  H01L21/28247 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

Abstract: The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the nitride spacers and the cap nitride are both removed by wet etching. Next, an ion implantation is carried out to dope dopants into the gate and in the N well. Doped regions for the NMOS device are next formed in the P well by performing a further ion implantation. An oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped oxide layer. An ultra-shallow source and drain junctions and the extended source and drain are obtained by using the amorphous silicon layer as a diffusion source. Next, nitrogen spacers on the side walls of the oxide are formed. The oxide on the top of the gate and uncovered by the spacers are removed during the etching to form spacers. Self-aligned silicide (SALICIDE) and polycide are respectively formed on the exposed substrate and gate.

Abstract translation: 本发明包括在栅极结构和衬底氧化物上形成氮掺杂非晶硅层。 氮化物间隔物形成在栅极结构的侧壁上。 然后，通过湿蚀刻去除氮化物间隔物和顶盖氮化物。 接下来，进行离子注入以将掺杂剂掺杂到栅极和N阱中。 接着通过进一步的离子注入在P阱中形成用于NMOS器件的掺杂区域。 进行氧化以将氮掺杂非晶硅层转换成氮掺杂氧化物层。 通过使用非晶硅层作为扩散源，获得了超浅的源极和漏极结以及扩展的源极和漏极。 接下来，形成氧化物侧壁上的氮隔离物。 在蚀刻期间，去除栅极顶部并被间隔物覆盖的氧化物以形成间隔物。 分别在暴露的基板和栅极上形成自对准的硅化物（SALICIDE）和多晶硅化物。

公开(公告)号：US6133101A

公开(公告)日：2000-10-17

申请号：US57867

申请日：1998-04-09

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238 ,  H01L21/8246 ,  H01L21/8236

CPC classification number: H01L27/11266 ,  H01L21/823814

Abstract: The present invention includes performing a blanket ion implantation to form lightly doped drain regions (LDD) adjacent to gate structures. A second ion implantation is performed with tilted angle to form p channel punchthrough stopping regions. A third ion implantation is used to implant ions into a NMOS device region. Oxide spacers are then formed on gate structures. Next, a forth ion implantation is then carried out to dope ions into the substrate to form source and drain regions in the NMOS region and a NMOS cell region, respectively. Next, a fifth ion implantation is used to dope dopant into a PMOS device region, thereby forming source and drain regions in the PMOS device region. Subsequently, a high temperature thermal anneal is performed to form shallow junction of the devices.

Abstract translation: 本发明包括执行毯式离子注入以形成与栅极结构相邻的轻掺杂漏极区（LDD）。 以倾斜角进行第二离子注入，形成p沟道穿通停止区域。 使用第三离子注入来将离子注入到NMOS器件区域中。 然后在栅极结构上形成氧化物间隔物。 接下来，然后进行第四次离子注入以将离子掺杂到衬底中，以在NMOS区域和NMOS单元区域中分别形成源区和漏区。 接下来，使用第五离子注入来将掺杂剂掺杂到PMOS器件区域中，从而在PMOS器件区域中形成源极和漏极区域。 随后，进行高温热退火以形成器件的浅结。

公开(公告)号：US6091098A

公开(公告)日：2000-07-18

申请号：US310890

申请日：1999-05-12

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L28/91 ,  H01L27/10852 ,  H01L28/84

Abstract: The capacitor of the present invention mainly includes the storage node 52, the capacitor dielectric layer 54, and the conductive layer 56. The storage node 52 is formed on the semiconductor substrate 30, and the storage node 52 includes a base member 52a, two vertical members 52b, two horizontal members 52c, and two sidewall members 52d, in which the base member 52a provides a conductive communication to an underlying conductive region in the substrate 30, the two vertical members 52b respectively extends upward from two lateral ends of the base member 52a, the two horizontal members 52c respectively and outwardly extends from two top ends of the two vertical members 52b, and the two sidewall members 52d respectively and upwardly extending from two outward ends of said two horizontal members 52c. The dielectric layer 54 is covered on the storage node 52 and the conductive layer 56 is formed on the dielectric layer 54.

Abstract translation: 本发明的电容器主要包括存储节点52，电容介质层54和导电层56.存储节点52形成在半导体衬底30上，存储节点52包括基底部件52a，两个垂直的 构件52b，两个水平构件52c和两个侧壁构件52d，其中基部构件52a提供与衬底30中的下面的导电区域的导电连通，两个垂直构件52b分别从基部构件的两个侧向端部向上延伸 如图52a所示，两个水平构件52c分别从两个垂直构件52b的两个顶端和两个侧壁构件52d分别向外延伸并且从所述两个水平构件52c的两个外端向上延伸。 电介质层54被覆盖在存储节点52上，导电层56形成在电介质层54上。

公开(公告)号：US6090663A

公开(公告)日：2000-07-18

申请号：US298929

申请日：1999-04-22

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/84 ,  H01L28/87

Abstract: In the preferred embodiment for forming a rugged polysilicon cup-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed on the first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are then removed to define an opening therein. A second conductive layer is formed conformably on the substrate within the opening and on the first conductive layer. A sidewall structure is then formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer. A third conductive layer is formed conformably on the substrate and formed to fill up the contact hole. Portions of the first conductive layer and the third conductive layer are removed to define a storage node. The second dielectric layer is then removed and a third dielectric layer is formed on the substrate. Finally, a fourth conductive layer is formed on the third dielectric layer to complete the formation of the capacitor.

Abstract translation: 在用于形成动态随机存取存储单元的粗糙多晶硅杯形电容器的优选实施例中，在半导体衬底上形成第一介电层。 第二电介质层形成在第一电介质层上，随后在第二电介质层上形成第一导电层。 然后去除第一导电层和第二介电层的部分以在其中限定开口。 第二导电层在开口内和第一导电层上的衬底上顺应地形成。 然后在第二导电层的侧壁上的开口内形成侧壁结构。 接下来，执行去除步骤以去除未被侧壁结构覆盖的第二导电层的一部分。 使用剩余的第二导电层作为掩模来去除侧壁结构和第一介电层的一部分，以限定第一介电层内的接触孔。 第三导电层在衬底上顺应地形成并形成以填充接触孔。 去除第一导电层和第三导电层的部分以限定存储节点。 然后去除第二电介质层，并在衬底上形成第三电介质层。 最后，在第三电介质层上形成第四导电层以完成电容器的形成。

公开(公告)号：US6081032A

公开(公告)日：2000-06-27

申请号：US23260

申请日：1998-02-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/535

CPC classification number: H01L21/7684 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/522 ,  H01L2924/0002

Abstract: An interconnection structure is disclosed. The interconnection structure has a dielectric layer over a semiconductor substrate. The interconnection structure also has first conductive connections within the dielectric layer. Second conductive connections are located over first conductive connections within the dielectric layer for connecting the first conductive connections. More layers of the interconnection structure can be stacked with the same structure to form multi-level connections.

Abstract translation: 公开了互连结构。 互连结构在半导体衬底上具有介电层。 互连结构还在电介质层内具有第一导电连接。 第二导电连接位于电介质层内的第一导电连接之上，用于连接第一导电连接。 互连结构的更多层可以以相同的结构堆叠以形成多层连接。

公开(公告)号：US6034403A

公开(公告)日：2000-03-07

申请号：US104533

申请日：1998-06-25

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8246 ,  H01L29/72

CPC classification number: H01L27/1126

Abstract: A high-density flat cell mask ROM is disclosed. The mask ROM comprises: a semiconductor substrate having a plurality of trenches and each of the trenches is separated to keep a space with each other. A plurality of oxynitride layers is formed on all sidewall and bottom surfaces of those trenches. A plurality of n+-doped polysilicon layers is formed on the oxynitride layers. A n+ doped silicon layer serves as buried bit line formed in the semiconductor substrate and surrounding the trenches. Each of the doped silicon layers is spaced from the n+-doped polysilicon layers by the oxynitride layer. A plurality of thick oxide layers is formed on the n+ polysilicon layers. A plurality of thin oxide layers are formed on the semiconductor substrate and between those thick oxide layer, and each of thin oxide layers is contiguous with the thick oxide layers. A coding region is formed in the semiconductor substrate and abutting one of those thin oxide layers, and another n+-doped polysilicon layer formed on upper surfaces of those thick oxide layers, and those thin oxide layers.

Abstract translation: 公开了一种高密度扁平单元掩膜ROM。 掩模ROM包括：具有多个沟槽的半导体衬底，并且每个沟槽被分离以保持彼此的空间。 在这些沟槽的所有侧壁和底表面上形成多个氧氮化物层。 在氮氧化物层上形成多个n +掺杂的多晶硅层。 n +掺杂硅层用作形成在半导体衬底中并围绕沟槽的掩埋位线。 每个掺杂硅层通过氮氧化物层与n +掺杂的多晶硅层间隔开。 在n +多晶硅层上形成多个厚的氧化物层。 多个薄氧化物层形成在半导体衬底上，并且在这些厚氧化物层之间，并且每个薄氧化物层与厚氧化物层相邻。 在半导体衬底中形成编码区域，并且邻接其中一个薄氧化物层，以及形成在这些厚氧化物层的上表面上的另一个n +掺杂多晶硅层以及那些薄氧化物层。