公开(公告)号：US5982730A

公开(公告)日：1999-11-09

申请号：US893486

申请日：1997-07-11

申请人： Makoto Matsuura ,  Takeshi Nakayama ,  Katsuaki Nakajima

发明人： Makoto Matsuura ,  Takeshi Nakayama ,  Katsuaki Nakajima

IPC分类号： G11B27/10 ,  G11B27/34 ,  G11B27/36 ,  G11B31/00

CPC分类号： G11B27/105 ,  G11B27/34 ,  G11B27/36 ,  G11B31/00

摘要： The on/off statuses of relays corresponding to information played back from an optical disk, for example, position information such as absolute time and track number, are stored in memory. When the absolute time or track number in the sub-code information decoded by the sub-code decode circuit is identical to the absolute time or track number stored in memory, the relays in the external device interface unit are switched to control the external devices connected to them. With this arrangement, external devices such as lights, slide projector, and illumination may easily be controlled in synchronization with optical disk playback information.

摘要翻译： 对应于从光盘播放的信息的继电器的开/关状态，例如绝对时间和轨道号等位置信息被存储在存储器中。 当由子码解码电路解码的子码信息中的绝对时间或轨道号与存储在存储器中的绝对时间或轨道号相同时，外部设备接口单元中的继电器被切换以控制连接的外部设备 给他们。 通过这种布置，可以容易地与光盘播放信息同步地控制诸如灯，幻灯机和照明的外部设备。

公开(公告)号：US5544117A

公开(公告)日：1996-08-06

申请号：US670543

申请日：1991-03-15

申请人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

发明人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C16/16

摘要： A non-volatile semiconductor memory device according to the present invention comprises a plurality of memory cells including floating gates, an injecting device for injecting electrons to the floating gate of each of the memory cells, a removing device for removing electrons from the floating gate of each of the memory cells, an erasure instructing device for instructing erasing operation, and a controlling device responsive to an instruction output from the erasure instructing device for controlling the injecting device such that electrons are simultaneously injected to all the floating gates of the memory cells which are to be erased before the removing operation by the removing device.

摘要翻译： 根据本发明的非易失性半导体存储器件包括多个存储单元，包括浮置栅极，用于向每个存储单元的浮置栅极注入电子的注入装置，用于从浮置栅极去除电子的去除装置 每个存储器单元，用于指示擦除操作的擦除指令装置，以及响应于从擦除指令装置输出的用于控制注入装置的指令的控制装置，使得电子同时注入到存储单元的所有浮动栅极， 在去除装置的去除操作之前被擦除。

公开(公告)号：US5402382A

公开(公告)日：1995-03-28

申请号：US942887

申请日：1992-09-10

申请人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

发明人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

IPC分类号： H01L21/8247 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/16

摘要： A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information charge, a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a high voltage generator for generating a negative high voltage. The high voltage generator is connected to each word line and has a capacitor to which a predetermined clock is applied in response to a signal for selecting word lines. The semiconductor memory device further comprises an erasing device, which applies the negative high voltage generated by, the high voltage generator to the word line selected by the selection signal in the erasing operation. The erasing device grounds the source line connected to the source of the corresponding memory cell.

摘要翻译： 非易失性半导体存储器件具有多个存储单元，它们以具有行和列的矩阵形式布置，并且各自具有用于保持信息电荷的栅极，多个位线，多个字线，多个 源极线和用于产生负高电压的高压发生器。 高电压发生器连接到每个字线，并且响应于用于选择字线的信号，具有施加预定时钟的电容器。 半导体存储器件还包括擦除器件，其在擦除操作中将由高电压发生器产生的负高电压施加到由选择信号选择的字线。 擦除装置将连接到相应存储单元的源的源极线接地。

公开(公告)号：US5371705A

公开(公告)日：1994-12-06

申请号：US066300

申请日：1993-05-24

申请人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

发明人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C17/00 ,  H02M3/07 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C5/143 ,  G11C16/12 ,  G11C16/30

摘要： The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

摘要翻译： 半导体器件包括用于在第一电源线上选择性地产生第一电平或第二电平的信号的电压发生器，以及使用第一电源线上的电压信号的电压转换器和用于产生电压信号的第二电源线 根据输入信号在第一或第二供电线上的电平;以及电压电平移位器，用于检测第一电源线上的电压电平，使电压电平将第二电源线上的信号移向第一电平 当第一电源线上的电压接近第一电平时。 可以减小第一和第二电源线上的电压差，以改善包括在电压转换器中的晶体管的分解特性，从而获得可靠的半导体器件。

公开(公告)号：US5363330A

公开(公告)日：1994-11-08

申请号：US826943

申请日：1991-01-28

申请人： Shinichi Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Yasushi Terada

发明人： Shinichi Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Yasushi Terada

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C2216/14

摘要： A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

摘要翻译： 消除了连接到每个位线的列锁存器和高压开关，并且新提供地址计数器和数据锁存器。 数据锁存器布置在I / O缓冲器和Y门之间。 在编程周期中，地址计数器被激活，并且连续选择Y门中的传输门。 因此，根据存储在数据锁存器中的写入数据，对存储单元阵列中的位线周期地施加高电压Vpp或0V。

公开(公告)号：USD338863S

公开(公告)日：1993-08-31

申请号：US691595

申请日：1991-04-25

申请人： Takeshi Nakayama

设计人： Takeshi Nakayama

公开(公告)号：US5233610A

公开(公告)日：1993-08-03

申请号：US574039

申请日：1990-08-29

申请人： Takeshi Nakayama ,  Yasushi Terada ,  Masanori Hayashikoshi ,  Kazuo Kobayashi ,  Yoshikazu Miyawaki

发明人： Takeshi Nakayama ,  Yasushi Terada ,  Masanori Hayashikoshi ,  Kazuo Kobayashi ,  Yoshikazu Miyawaki

IPC分类号： G11C29/00 ,  G06F11/00 ,  G06F11/10 ,  G11C17/00 ,  G11C29/20 ,  G11C29/42

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C29/20 ,  G06F11/076

摘要： A semiconductor memory device comprises a memory array, a test mode detecting circuit, an address counter, a correction circuit, and a data counter. When a test mode enable signal is applied externally to the test mode detecting circuit, the address counter sequentially addresses the memory array. The correction circuit detects the error of the data sequentially read out from the memory array. The data counter counts the number of data to be corrected by said correction circuit. The counting result is outputted to the exterior.

摘要翻译： 半导体存储器件包括存储器阵列，测试模式检测电路，地址计数器，校正电路和数据计数器。 当在测试模式检测电路外部施加测试模式使能信号时，地址计数器顺序地寻址存储器阵列。 校正电路检测从存储器阵列顺序读出的数据的错误。 数据计数器对由所述校正电路校正的数据的数量进行计数。 计数结果输出到外部。

公开(公告)号：US5111427A

公开(公告)日：1992-05-05

申请号：US310115

申请日：1989-02-14

申请人： Kazuo Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama

发明人： Kazuo Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama

IPC分类号： G11C15/04

CPC分类号： G11C15/046 ,  G11C15/043

摘要： Each of memory cells in a nonvolatile content-addressable memory (CAM) comprises a first memory transistor connected to a first storage node, a second memory transistor connected to a second storage node, and a memory capacitor connected between said first and second storage nodes. The first storage node is connected to a first bit line through an MOS transistor, and the second storage node is connected to a second bit line through the MOS transistor. In addition, each of the memory cells has a function of determining whether or not information applied to the first and second bit lines and information applied to the first and second storage nodes match with each other. In the nonvolatile CAM, writing and reading by a DRAM operation become possible by using the memory capacitor in each of the memory cells. In addition, in the nonvolatile CAM, nonvolatile writing and reading by an EEPROM operation become possible by using the first and second memory transistors in each of the memory cells. Furthermore, information stored in the memory capacitor or the first and second memory transistors in each of the memory cells can be searched by applying search information to the corresponding first and second bit line pairs.

摘要翻译： 非易失性内容寻址存储器（CAM）中的每个存储器单元包括连接到第一存储节点的第一存储器晶体管，连接到第二存储节点的第二存储晶体管和连接在所述第一和第二存储节点之间的存储电容器。 第一存储节点通过MOS晶体管连接到第一位线，并且第二存储节点通过MOS晶体管连接到第二位线。 此外，每个存储单元具有确定施加到第一和第二位线的信息以及应用于第一和第二存储节点的信息是否彼此匹配的功能。 在非易失性CAM中，通过使用每个存储单元中的存储电容器，可以通过DRAM操作进行写入和读取。 此外，在非易失性CAM中，通过使用每个存储单元中的第一和第二存储晶体管，可以通过EEPROM操作进行非易失性写入和读取。 此外，可以通过将搜索信息应用于对应的第一和第二位线对来搜索存储在每个存储器单元中的存储电容器或第一和第二存储器晶体管中的信息。

公开(公告)号：US5022009A

公开(公告)日：1991-06-04

申请号：US310116

申请日：1989-02-14

申请人： Yasushi Terada ,  Takeshi Nakayama ,  Kazuo Kobayashi

发明人： Yasushi Terada ,  Takeshi Nakayama ,  Kazuo Kobayashi

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  G11C16/28

CPC分类号： G11C16/16 ,  G11C16/0425 ,  G11C16/28

摘要： First and second bit lines are arranged on one side of each sense amplifier while third and fourth bit lines are arranged on the other side thereof. A first dummy cell is connected to either the first bit line or the second bit line. In addition, a second dummy cell is connected to either the third bit line or the fourth bit line. When a memory cell connected to the first bit line is selected, the second dummy cell is simultaneously selected. On this occasion, the first bit line is connected to a first terminal of the sense amplifier, and the third bit line and the fourth bit line are connected to a second terminal of the sense amplifier. Potentials of the first and second terminals are differentially amplified. On the other hand, when a memory cell connected to the third bit line is selected, the first dummy cell is simultaneously selected. On this occasion, the third bit line is connected to the second terminal of the sense amplifier, and the first bit line and the second bit line are connected to the first terminal of the sense amplifier. The potentials of the first and second terminals are differentially amplified.

摘要翻译： 第一和第二位线布置在每个读出放大器的一侧上，而第三和第四位线布置在其另一侧上。 第一虚拟单元连接到第一位线或第二位线。 此外，第二虚拟单元连接到第三位线或第四位线。 当选择连接到第一位线的存储单元时，同时选择第二虚设单元。 在这种情况下，第一位线连接到读出放大器的第一端，第三位线和第四位线连接到读出放大器的第二端。 第一和第二端子的电位差分放大。 另一方面，当选择连接到第三位线的存储单元时，同时选择第一虚设单元。 在这种情况下，第三位线连接到读出放大器的第二端，第一位线和第二位线连接到读出放大器的第一端。 第一和第二端子的电位差分放大。

公开(公告)号：US4903236A

公开(公告)日：1990-02-20

申请号：US156431

申请日：1988-02-16

申请人： Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

发明人： Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

IPC分类号： G11C16/10

CPC分类号： G11C16/10

摘要： In an erase mode, a high DC voltage Vpp is applied to all of the word lines and zero volt is applied to all of the bit lines, whereby the contents of all of the memory transistors are simultaneously erased. In a write mode, which constitutes an essential feature of the present invention, zero volt is applied to a selected word line and the high DC voltage Vpp is applied to a selected bit line, with an intermediate voltage 1/2.Vpp being applied to the other word lines and bit lines. Thus, by electron tunneling, data is written in a memory transistor located at a point of intersection between the selected word line and the selected bit line.

摘要翻译： 在擦除模式中，对所有字线施加高直流电压Vpp，并且零电压施加到所有位线，由此所有存储晶体管的内容同时被擦除。 在构成本发明的基本特征的写入模式中，零电压被施加到所选字线，并且高直流电压Vpp被施加到所选择的位线，中间电压1 / 2.Vpp被施加到 其他字线和位线。 因此，通过电子隧穿，将数据写入位于所选字线和所选位线之间的交点处的存储晶体管中。