公开(公告)号：US08687421B2

公开(公告)日：2014-04-01

申请号：US13435476

申请日：2012-03-30

申请人： Chris Avila ,  Jianmin Huang ,  Dana Lee

发明人： Chris Avila ,  Jianmin Huang ,  Dana Lee

IPC分类号： G11C16/00

CPC分类号： G06F11/1048 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/5634

摘要： The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected.

摘要翻译： 是否刷新或退出内存块的决定是基于正在使用的一组动态读取值。 在使用动态读取值表的存储器系统中，该表被配置为包括如何处理读取错误（退出，刷新）以及不同动态读取情况的读取参数。 在细化中，读取案例编号可用于对被选择进行刷新或退出的块进行优先级排序。 在读取擦除更精确的情况下，可以应用多个动态读取情况。 此外，可以智能地选择应用哪些情况。

公开(公告)号：US08472266B2

公开(公告)日：2013-06-25

申请号：US13077778

申请日：2011-03-31

申请人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

发明人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

摘要翻译： 公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。 技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。 例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。 在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。 将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

公开(公告)号：US20130051148A1

公开(公告)日：2013-02-28

申请号：US13214765

申请日：2011-08-22

申请人： Dana Lee ,  Ken Oowada

发明人： Dana Lee ,  Ken Oowada

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C11/5642

摘要： Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.

摘要翻译： 提供了部分编程的非易失性存储块的读取补偿。 在部分编程的块中，阈值电压分布可以相对于其最终位置向下移动。 在接收到读取存储在块中的页面的请求时，可以确定块是否被部分编程。 如果是这样，那么在阅读请求的页面时可以做出适当的补偿。 该补偿可以补偿块中尚未编程的非易失性存储元件（或页）。 补偿金额可以基于通过稍后对其他页面进行编程而对所请求的页面造成的干扰量。 该补偿可以补偿所请求的页面的阈值电压分布的变化，其将从其他页面的后续编程发生。

公开(公告)号：US20120250414A1

公开(公告)日：2012-10-04

申请号：US13077778

申请日：2011-03-31

申请人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

发明人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

摘要翻译： 公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。 技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。 例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。 在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。 将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

公开(公告)号：US20120008384A1

公开(公告)日：2012-01-12

申请号：US12833146

申请日：2010-07-09

申请人： Yan Li ,  Dana Lee ,  Jonathan Huynh

发明人： Yan Li ,  Dana Lee ,  Jonathan Huynh

IPC分类号： G11C16/06

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5006

摘要： Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit.

摘要翻译： 提供技术和相应的电路用于检测存储器阵列中的字线泄漏。 在示例性实施例中，使用电容分压器将高压降转换成可与参考电压进行比较的低电压降，以确定由于泄漏引起的电压降。 片上自校准方法可以帮助确保这种检测泄漏极限的技术的准确性。

公开(公告)号：US20110310671A1

公开(公告)日：2011-12-22

申请号：US13221147

申请日：2011-08-30

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

公开(公告)号：US20110260235A1

公开(公告)日：2011-10-27

申请号：US12887328

申请日：2010-09-21

申请人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

发明人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28291 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/788

摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

摘要翻译： 公开了非电压存储和用于制造非易失性存储器的技术。 在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。 在一个实施例中，控制栅极的下部是p型多晶硅。 控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。 因此，如果控制门耗尽，可能会发生的一些问题得到缓解。 例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

公开(公告)号：US07915124B2

公开(公告)日：2011-03-29

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

公开(公告)号：US07894263B2

公开(公告)日：2011-02-22

申请号：US11864825

申请日：2007-09-28

申请人： Dana Lee ,  Hock So

发明人： Dana Lee ,  Hock So

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418 ,  G11C2211/565

摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

摘要翻译： 使用源侧热电子注入编程非易失性存储器。 为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。 在充电之后，将第二低电压施加到与选定位线相邻的未选位线。 由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。 用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

公开(公告)号：US07869273B2

公开(公告)日：2011-01-11

申请号：US11849992

申请日：2007-09-04

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。