公开(公告)号：US06795326B2

公开(公告)日：2004-09-21

申请号：US10017664

申请日：2001-12-12

申请人： Christophe Chevallier

发明人： Christophe Chevallier

IPC分类号： G11C700

CPC分类号： G11C29/025 ,  G11C7/18 ,  G11C29/02 ,  H01L27/115

摘要： A flash memory device that has a global and local bit line design that enables an alternate bit line stress mode as well as a way to detect short circuits in local and global bit lines with a single alternate bit line program. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

摘要翻译： 具有全局和局部位线设计的闪速存储器件，能够实现备用位线应力模式，以及通过单个备用位线程序检测局部和全局位线中的短路的方法。 闪速存储器件具有多组相邻的局部位线，多个全局位线和多个选择晶体管。 每个选择晶体管具有控制栅极，并且耦合在每组局部位线中的局部位线之一和全局位线之一中。 因此，每组局部位线中的每个局部位线被耦合到不同的全局位线。 多个选择线用于激活选择晶体管上的控制栅极。 每个选择线耦合到相关选择晶体管上的控制栅极。 相关联的选择晶体管是选择晶体管，其耦合到相关联的局部位线集合中的局部位线。

公开(公告)号：US06769103B2

公开(公告)日：2004-07-27

申请号：US10199727

申请日：2002-07-19

申请人： Christophe Chevallier ,  Adriana Ababei

发明人： Christophe Chevallier ,  Adriana Ababei

IPC分类号： G06F1750

CPC分类号： G06F17/5081

摘要： A method for checking the accuracy of non-standard line widths in a layout includes marking lines with a line width marker, and associating the line width markers with the lines throughout a design process to ensure that the lines remain at the desired widths.

公开(公告)号：US5387014A

公开(公告)日：1995-02-07

申请号：US135229

申请日：1993-10-12

申请人： Christophe Chevallier

发明人： Christophe Chevallier

IPC分类号： B60H1/32 ,  B60H1/00 ,  F16L3/223 ,  F16L39/00 ,  F25B41/00 ,  F16L41/12

CPC分类号： B60H1/00571 ,  F16L3/223 ,  F16L39/00 ,  F25B41/003

摘要： A motor vehicle air conditioning installation includes a pair of parallel tubes with annular beads at their free ends, for assembly to a component of the fluid circuit of the installation, and a clamping plate or strut connecting the two tubes together. The strut is an elongated plate having two through apertures. One of these is a notch open at one end of the plate. Each aperture has a substantially semicircular region matching the circumference of the associated tubular element fitting within it. The second aperture is surrounded by the material of the plate over its whole periphery, and includes a widened region through which the associated bead of the corresponding tubular element can pass, this widened region being joined directly to the substantially semicircular region. The strut cannot be separated from the tubes without resilient deformation of the latter, which avoids the danger of its becoming lost during disassembly.

摘要翻译： 机动车空调装置包括一对平行管，其自由端具有环形小珠，用于组装到装置的流体回路的部件，以及将两个管连接在一起的夹板或支柱。 支柱是具有两个通孔的细长板。 其中一个是在板的一端开口的开口。 每个孔具有与其内的相关联的管状元件配件的圆周匹配的大致半圆形区域。 第二孔被其整个周边的板的材料包围，并且包括加宽的区域，相应管状元件的相关联的珠可以穿过该加宽区域，该加宽区域直接连接到大致半圆形区域。 支柱不能与管分离而没有弹性变形，这避免了在拆卸过程中其损失的危险。

公开(公告)号：US08682331B2

公开(公告)日：2014-03-25

申请号：US12702714

申请日：2010-02-09

申请人： Sumeeth Nagaraja ,  Mehmet Yavuz ,  Farhad Meshkati ,  Christophe Chevallier

发明人： Sumeeth Nagaraja ,  Mehmet Yavuz ,  Farhad Meshkati ,  Christophe Chevallier

IPC分类号： H04W36/00 ,  H04W72/00 ,  H04W4/00 ,  H04W68/00 ,  H04M11/00

CPC分类号： H04W36/30 ,  H04W84/045

摘要： Various systems and methods for interference beacon transmission are disclosed. In one embodiment, an apparatus for initiating cell reselection in a wireless communication device, such as a HNB, comprises a processor configured to determine a first frequency at which one or more wireless communication devices communicate with a first cell and a transceiver configured to transmit an interference beacon at the first frequency configured to at least partially interfere with communications at the first frequency and initiate a cell reselection process by at least one of the wireless communication devices.

摘要翻译： 公开了用于干扰信标传输的各种系统和方法。 在一个实施例中，用于在无线通信设备（例如HNB）中发起小区重选的设备包括处理器，其被配置为确定一个或多个无线通信设备与第一小区通信的第一频率和被配置为发送 第一频率的干扰信标被配置为至少部分地干扰在第一频率的通信，并且由至少一个无线通信设备发起小区重选过程。

公开(公告)号：US08577378B2

公开(公告)日：2013-11-05

申请号：US12697040

申请日：2010-01-29

申请人： Sumeeth Nagaraja ,  Mehmet Yavuz ,  Farhad Meshkati ,  Andrei D. Radulescu ,  Christophe Chevallier

发明人： Sumeeth Nagaraja ,  Mehmet Yavuz ,  Farhad Meshkati ,  Andrei D. Radulescu ,  Christophe Chevallier

IPC分类号： H04W36/00 ,  H04W4/00

CPC分类号： H04W36/0061 ,  H04W36/0005 ,  H04W36/04 ,  H04W36/16 ,  H04W84/045

摘要： Methods, apparatuses, and computer program products are disclosed for facilitating a beacon-assisted handover from a macro network to a femto cell during an active call. A femto cell management system assigns a unique identifier to a femto cell, which the femto cell utilizes to broadcast a beacon at a frequency different than the operating frequency of the femto cell. A wireless terminal receives a control message from the macro network directing the wireless terminal to scan particular frequencies. The wireless terminal subsequently provides a report to the macro network identifying attributes ascertained from the scan, which includes attributes associated with the beacon. The macro network then performs a handover from the macro network to the femto cell as a function of the attributes.

摘要翻译： 公开了方法，装置和计算机程序产品，用于促进在活动呼叫期间从宏网络到毫微微小区的信标辅助切换。 毫微微小区管理系统向毫微微小区分配唯一标识符，毫微微小区利用毫微微小区以与毫微微小区的工作频率不同的频率广播信标。 无线终端从宏网络接收指示无线终端扫描特定频率的控制消息。 无线终端随后向宏网络提供识别从扫描确定的属性的报告，其包括与信标相关联的属性。 然后，宏网络根据属性执行从宏网络到毫微微小区的切换。

公开(公告)号：US20120257438A1

公开(公告)日：2012-10-11

申请号：US13530009

申请日：2012-06-21

申请人： Chang Hua Siau ,  Christophe Chevallier

发明人： Chang Hua Siau ,  Christophe Chevallier

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/3418 ,  G11C16/3431 ,  G11C2013/0054 ,  G11C2211/5634 ,  G11C2211/5646 ,  G11C2213/71 ,  G11C2213/77

摘要： Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

摘要翻译： 公开了用于恢复可重写非易失性存储器中的数据值的电路。 集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。 每个存储器阵列包括多个两端存储元件。 可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。 此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储元件的读取余量，由此提供同时的读取和余量确定操作。 从两端存储元件读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或 硬擦除状态）。

公开(公告)号：US08271014B2

公开(公告)日：2012-09-18

申请号：US12536896

申请日：2009-08-06

申请人： Aziz Gholmieh ,  Farhad Meshkati ,  Mehmet Yavuz ,  Siddharth Mohan ,  Christophe Chevallier

发明人： Aziz Gholmieh ,  Farhad Meshkati ,  Mehmet Yavuz ,  Siddharth Mohan ,  Christophe Chevallier

IPC分类号： H04B7/00

CPC分类号： H04W52/10 ,  H04W52/244 ,  H04W52/246 ,  H04W52/367

摘要： A small base node such as a Home Base Node (HNB), or femto cell, may reduce its transmit power in order to prevent co-channel or adjacent channel interference, or to limit its coverage area. Once the power is set, the HNB signal to a served Home User Equipment (HUE) its transmit Common Pilot Channel (CPICH) transmit power for accurate path loss estimation. When this power is outside of the permissible range, the HNB adjusts other parameters (such as Random Access Channel (RACH) constant value) to compensate for the error in signaled CPICH power, and thus compensate in that process the error in determining path loss. Similarly, if the uplink sensitivity is adjusted, to prevent interference, parameters would also be adjusted and signaled to the HUE to reflect the link imbalance.

摘要翻译： 诸如家庭基站节点（HNB）或毫微微小区之类的小型基站节点可以降低其发射功率，以防止同信道或相邻信道干扰，或限制其覆盖区域。 一旦功率被设置，HNB信号到服务的家庭用户设备（HUE），其发射公共导频信道（CPICH）发送功率用于精确的路径损耗估计。 当该功率超出允许范围时，HNB调整其他参数（如随机接入信道（RACH）常数值）来补偿信令CPICH功率中的误差，从而在该过程中补偿确定路径损耗的误差。 类似地，如果调整上行链路灵敏度，为了防止干扰，参数也将被调整并发出信号到HUE以反映链路不平衡。

公开(公告)号：US20110188289A1

公开(公告)日：2011-08-04

申请号：US12657895

申请日：2010-01-29

申请人： Christophe Chevallier ,  Chang Hua Siau

发明人： Christophe Chevallier ,  Chang Hua Siau

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

摘要翻译： 本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器 直接位于包含数据访问电路的FEOL基板之上。 在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。 访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。 修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

公开(公告)号：US20110080763A1

公开(公告)日：2011-04-07

申请号：US12927247

申请日：2010-11-09

申请人： Chang Hua Siau ,  Christophe Chevallier

发明人： Chang Hua Siau ,  Christophe Chevallier

IPC分类号： G11C5/02 ,  G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/3418 ,  G11C16/3431 ,  G11C2013/0054 ,  G11C2211/5634 ,  G11C2211/5646 ,  G11C2213/71 ,  G11C2213/77

摘要： Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

摘要翻译： 公开了用于恢复非易失性存储器中的数据值的电路和方法。 集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。 每个存储器阵列包括多个两端存储单元。 可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。 此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储器单元的读取余量，从而提供同时的读取和余量确定操作。 从两端存储单元读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或 硬擦除状态）。

公开(公告)号：US20100203890A1

公开(公告)日：2010-08-12

申请号：US12697040

申请日：2010-01-29

申请人： Sumeeth Nagaraja ,  Mehmet Yavuz ,  Farhad Meshkati ,  Andrei D. Radulescu ,  Christophe Chevallier

发明人： Sumeeth Nagaraja ,  Mehmet Yavuz ,  Farhad Meshkati ,  Andrei D. Radulescu ,  Christophe Chevallier

IPC分类号： H04W36/00

CPC分类号： H04W36/0061 ,  H04W36/0005 ,  H04W36/04 ,  H04W36/16 ,  H04W84/045

摘要： Methods, apparatuses, and computer program products are disclosed for facilitating a beacon-assisted handover from a macro network to a femto cell during an active call. A femto cell management system assigns a unique identifier to a femto cell, which the femto cell utilizes to broadcast a beacon at a frequency different than the operating frequency of the femto cell. A wireless terminal receives a control message from the macro network directing the wireless terminal to scan particular frequencies. The wireless terminal subsequently provides a report to the macro network identifying attributes ascertained from the scan, which includes attributes associated with the beacon. The macro network then performs a handover from the macro network to the femto cell as a function of the attributes.

摘要翻译： 公开了方法，装置和计算机程序产品，用于促进在活动呼叫期间从宏网络到毫微微小区的信标辅助切换。 毫微微小区管理系统向毫微微小区分配唯一标识符，毫微微小区利用毫微微小区以与毫微微小区的工作频率不同的频率广播信标。 无线终端从宏网络接收指示无线终端扫描特定频率的控制消息。 无线终端随后向宏网络提供识别从扫描确定的属性的报告，其包括与信标相关联的属性。 然后，宏网络根据属性执行从宏网络到毫微微小区的切换。