公开(公告)号：US20080215802A1

公开(公告)日：2008-09-04

申请号：US12054310

申请日：2008-03-24

申请人： David Q. Chow ,  I-Kang Yu ,  Siew Sin Hiew ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  I-Kang Yu ,  Siew Sin Hiew ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G11C13/0004

摘要： High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically.

摘要翻译： 公开了非易失性存储器件（NVMD）的高集成度。 根据本发明的一个方面，非易失性存储器件包括智能非易失性存储器（NVM）控制器和智能非易失性存储器模块。 NVM控制器包括一个中央处理单元（CPU），用于处理对NVM模块的数据传输操作，以确保源同步接口，交错数据操作和块抽象寻址。 智能NVM模块包括接口逻辑，块地址管理器和至少一个非易失性存储器阵列。 接口逻辑被配置为处理物理块管理。 块地址管理器被配置为确保将物理地址转换为智能NVM控制器的CPU可访问的转换地址。 变换后的地址可以是逻辑上或物理上的块，页，扇区或字节中的地址。

公开(公告)号：US20080209114A1

公开(公告)日：2008-08-28

申请号：US12101877

申请日：2008-04-11

申请人： David Q. Chow ,  I-Kang Yu ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  I-Kang Yu ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/123 ,  G06F2212/2022

摘要： Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address. Data programming and erasing are performed in a zone basis.

摘要翻译： 描述了具有基于区域的非易失性存储器文件系统的改进的可靠性高耐久性非易失性存储器件。 根据本发明的一个方面，基于区域的非易失性存储器文件系统包括两级地址映射方案：第一级地址映射方案将从主计算机系统接收的线性或逻辑地址映射到虚拟区域地址 ; 并且第二级地址映射方案将虚拟区域地址映射到非易失性存储器模块的物理区域地址。 虚拟区域地址表示多个区域，每个区域包括多个数据扇区。 区域被配置为小于数据块并且大于数据页的单元。 每个数据扇区由512字节的数据组成。 区域和扇区之间的比例由非易失性存储器模块的物理特性预先确定。 跟踪表用于将虚拟区域地址与物理区域地址相关联。 以区域为基础进行数据编程和擦除。

公开(公告)号：US20080209112A1

公开(公告)日：2008-08-28

申请号：US12035398

申请日：2008-02-21

申请人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/123 ,  G06F2212/7203 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5641 ,  G11C2211/5643

摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

摘要翻译： 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。

公开(公告)号：US20080185694A1

公开(公告)日：2008-08-07

申请号：US11872588

申请日：2007-10-15

申请人： Siew Sin Hiew ,  Jim Chin-Nan Ni ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： Siew Sin Hiew ,  Jim Chin-Nan Ni ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： G06F1/1632 ,  H01L2924/0002 ,  H01L2924/00

摘要： Portable electronic storage device (PESD) manufacturing methods utilizing lead frames are described. According to one exemplary embodiment, a process of manufacturing core unit of PESD comprises: producing a processed flash memory IC chip with several metal contact pads and at least one passive component located on top layer; pre-fabricating a lead frame having opposing first and second surfaces, a plurality of metal connectors disposed on the first surface and a cavity through both surfaces; attaching the top layer of the processed flash memory IC chip onto the first surface such that the metal connectors are electrically connected to the respective metal contact pads and the cavity provides an non-conductive space for the at least one passive component; and forming a molded enclosure on both surfaces of the lead frame to form a core unit, the mold enclosure is configured such that the connectors are exposed according to one of the PESD standards.

摘要翻译： 描述了利用引线框架的便携式电子存储装置（PESD）制造方法。 根据一个示例性实施例，制造PESD的核心单元的过程包括：产生具有多个金属接触焊盘的处理闪存IC芯片和位于顶层上的至少一个无源部件; 预先制造具有相对的第一和第二表面的引线框架，设置在第一表面上的多个金属连接器和通过两个表面的空腔; 将处理的闪存IC芯片的顶层附着到第一表面上，使得金属连接器电连接到相应的金属接触焊盘，并且空腔为至少一个无源部件提供非导电空间; 以及在所述引线框架的两个表面上形成模塑外壳以形成芯部单元，所述模具外壳被配置成使得所述连接器根据PESD标准之一而被暴露。

公开(公告)号：US20080071975A1

公开(公告)日：2008-03-20

申请号：US11929810

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080071974A1

公开(公告)日：2008-03-20

申请号：US11929730

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080071931A1

公开(公告)日：2008-03-20

申请号：US11929756

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/38

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080046635A1

公开(公告)日：2008-02-21

申请号：US11849344

申请日：2007-09-03

申请人： Ming-Shiang Shen

发明人： Ming-Shiang Shen

IPC分类号： G06F13/00

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so as to establish communication with the data terminal. The processing unit is operable selectively in a programming mode and a data retrieving mode. The electronic data storage medium also includes a function key set for manually switching the electronic data storage medium between the programming mode and the data retrieving mode.

公开(公告)号：US20080005581A1

公开(公告)日：2008-01-03

申请号：US11900937

申请日：2007-09-13

申请人： Ming-Shiang Shen

发明人： Ming-Shiang Shen

IPC分类号： H04K1/00

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so as to establish communication with the data terminal. The processing unit is operable selectively in a programming mode and a data retrieving mode. The electronic data storage medium also includes a function key set for manually switching the electronic data storage medium between the programming mode and the data retrieving mode.

公开(公告)号：US20080003883A1

公开(公告)日：2008-01-03

申请号：US11846733

申请日：2007-08-29

申请人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

发明人： Jim Ni ,  Abraham Ma ,  Paul Hsueh ,  Ming-Shiang Shen

IPC分类号： H01R13/66

CPC分类号： G06K19/07743 ,  A45C2011/188 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G06K19/077 ,  G06K19/07732 ,  G07C9/00087 ,  H05K1/117 ,  H05K1/118 ,  H05K1/189 ,  H05K3/284 ,  H05K3/4691 ,  H05K2201/091 ,  H05K2201/10159 ,  H05K2203/1527

摘要： A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an external Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Dividers between openings in the upper case that expose the SD contact pads also support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline. A metal switch-bar or an over-molded controller die may be substituted.

摘要翻译： 闪存设备具有印刷电路板组件（PCBA），PCB组件具有闪存芯片和控制器芯片。 控制器芯片包括一个外部安全数字（SD）接口，以及一个处理单元，用于从闪存芯片中读取数据块。 PCBA被封装在上壳体和下壳体内，PCB上的SD接触垫通过上壳体中的接触开口配合。 暴露SD接触垫的上壳体中的开口之间的分隔线也以与设备中心线倾斜的角度支撑PCB。 PCB在远端向上倾斜以允许安装到PCB的底表面的芯片具有更大的厚度，并且在插入端向下倾斜以将SD接触垫定位在中心线附近。 金属开关杆或过模制的控制器管芯可以被替代。