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91.发明申请Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology 失效用于屏蔽隧道电路和浮栅的方法和装置，用于在通用CMOS技术中集成浮栅参考电压公开(公告)号：US20080044973A1
公开(公告)日：2008-02-21
申请号：US11639658
申请日：2006-12-14
IPC分类号： H01L21/336
CPC分类号： G11C27/005 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/7883
摘要： A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a floating gate shield layer so as to enclose the floating gate. The floating gate includes a first floating gate portion over an active area in the first doped well region and a second floating gate portion over the active area in the second doped well region. The first floating gate portion is substantially smaller than the second floating gate portion so as to enable adequate voltage coupling for Fowler-Nordheim tunneling to occur between the first doped well region and the first floating gate portion. The direction of tunneling is determined by high voltage application to one of the doped well regions.
摘要翻译： 一种用于屏蔽浮动栅极隧道元件的方法和相应的结构。 该方法包括使用在由场氧化物包围的衬底中形成的第一和第二掺杂阱区域限定的两个有源区域中的标准CMOS处理在栅极氧化物上设置浮置栅极，以及形成浮置栅极屏蔽层以便包围浮置栅极 。 浮置栅极包括在第一掺杂阱区域中的有源区域上的第一浮动栅极部分和位于第二掺杂阱区域中的有源区域上的第二浮动栅极部分。 第一浮栅部分基本上小于第二浮栅部分，以便能够在第一掺杂阱区域和第一浮栅部分之间产生用于Fowler-Nordheim隧道的足够的电压耦合。 通过高压施加到掺杂阱区之一来确定隧道的方向。
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公开(公告)号：US06645803B1
公开(公告)日：2003-11-11
申请号：US08713083
申请日：1996-09-12
申请人： Alexander Kalnitsky , Arnaud Lepert
发明人： Alexander Kalnitsky , Arnaud Lepert
IPC分类号： H01L218234
CPC分类号： H01L28/20 , H01C17/26 , H01L21/28061 , H01L21/321
摘要： A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be applied to the fabrication of an adjustable resistor or a MOS transistor having an adjustable threshold.
摘要翻译： 一种用于修改掺杂硅层的掺杂水平的方法，包括以下步骤：用难熔金属制成的硅化物层涂覆硅层，并将硅和硅化物之间的界面区域加热至预定温度。 该方法可以应用于具有可调阈值的可调电阻器或MOS晶体管的制造。
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公开(公告)号：US06593640B1
公开(公告)日：2003-07-15
申请号：US10114526
申请日：2002-04-01
IPC分类号： H01L27082
CPC分类号： H01L29/1004 , H01L29/161 , H01L29/167
摘要： A bipolar transistor comprises a base region and an an extrinsic base region being located generally adjacent to the base region. The extrinsic base region has implanted therein a dopant and a dopant diffusion-retarding substance. The dopant diffusion-retarding substance serves to reduce the diffusion of the dopant into the base region. Preferably, the dopant and diffusion-retarding substances are implanted such that there is a buffer zone in the extrinsic base region immediately adjacent to the base region into which the dopant may diffuse after implantation. The dopant may for example be boron, and the dopant diffusion-retarding substance may for example be a group IV element such as carbon or germanium.
摘要翻译： 双极晶体管包括基本区域和大致相邻于基极区域的非本征基极区域。 外部基极区域注入掺杂剂和掺杂剂扩散阻滞物质。 掺杂剂扩散阻滞物质用于减少掺杂剂扩散到基极区域中。 优选地，注入掺杂剂和扩散阻滞物质，使得在植入后掺杂剂可以扩散的基极区域紧邻的外在碱性区域中存在缓冲区。 掺杂剂可以例如是硼，并且掺杂剂扩散阻滞物质可以例如是IV族元素，例如碳或锗。
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94.发明授权Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation 有权在具有浅沟槽隔离的平坦化工艺中形成集成电感器和高速互连的方法公开(公告)号：US06593200B2
公开(公告)日：2003-07-15
申请号：US09989649
申请日：2001-11-20
IPC分类号： H01L21331
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and ‘cross-talk’ between conductors are substantially reduced. The resulting semiconductor device is also disclosed.
摘要翻译： 一种形成具有电感器和/或高速互连的半导体器件的方法。 该方法包括在衬底上形成外延层，形成穿过外延层的开口以暴露衬底的下部区域，在外延层的开口内形成第一电介质材料，使第一电介质层平坦化，形成第二电介质 材料层，然后在外延层的开口上方的第二介电材料层上形成金属化电感器。 在这种情况下，由于电感器和高速互连不会覆盖在导电外延层上，电感器的Q因子的劣化，高速互连的损耗特性和导体之间的“串扰”大大降低 还公开了所得到的半导体器件。
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95.发明授权公开(公告)号：US06380571B1
公开(公告)日：2002-04-30
申请号：US09173276
申请日：1998-10-14
IPC分类号： H01L31113
CPC分类号： H01L27/14654 , H01L27/14609 , H01L27/1463
摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.
摘要翻译： 具有门控二极管和读出晶体管的像素单元上的电位在图像积分周期之前被设置为初始电平。 在图像积分期间，吸收的光子导致像素单元的电位发生变化。 在图像积分周期之后，通过向门控二极管施加多个脉冲来复位和读出像素单元。 每个脉冲导致固定量的电荷注入到电池中。 当电池上的电位再次恢复到初始电平时，通过计算将电位恢复到初始电平所需的脉冲数来确定吸收光子的数量。 读出晶体管用于通过偏置晶体管来输出对应于像素单元上的电位的电流来确定电位何时处于初始电平。
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96.发明授权Method for forming an array of sidewall-contacted antifuses having diffused bit lines 有权用于形成具有扩散位线的侧壁接触反熔丝阵列的方法公开(公告)号：US06277724B1
公开(公告)日：2001-08-21
申请号：US09233370
申请日：1999-01-19
IPC分类号： H01L2144
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The method forms a plurality of spaced-apart bit lines in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are then formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word lines include a dielectric layer and an overlying layer of conductive material.
摘要翻译： 通过一种降低阵列对屏蔽对准误差的灵敏度的方法形成侧壁接触的反熔丝阵列。 该方法在半导体材料中形成多个间隔开的位线。 绝缘触点的行和列形成在半导体材料上，使得每个位线通过绝缘接触多次接触。 在每排触点中，每个触点具有暴露的侧壁。 然后在触点上形成多个字线，使得在一排暴露的侧壁中的每个暴露的侧壁上形成字线。 字线包括电介质层和导电材料的上覆层。
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97.发明授权Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor 有权利用肖特基二极管来增加晶体管的阈值电压的长沟道MOS晶体管公开(公告)号：US06262460B1
公开(公告)日：2001-07-17
申请号：US09480722
申请日：2000-01-07
IPC分类号： H01L2972
CPC分类号： H01L27/0629
摘要： When the threshold voltage of a long-channel transistor is set during the same dopant step of a manufacturing process that sets the threshold voltage of a short-channel transistor, the threshold voltage of the long-channel transistor is increased by connecting the long-channel transistor in series with a schottky diode.
摘要翻译： 当在设定短沟道晶体管的阈值电压的制造过程的相同掺杂剂步骤期间设置长沟道晶体管的阈值电压时，通过连接长沟道晶体管的阈值电压来增加长沟道晶体管的阈值电压 晶体管与肖特基二极管串联。
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98.发明授权I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection 有权使用一对阱结构作为电阻延迟ESD事件的I / O电路和用于ESD保护的二极管公开(公告)号：US06184557B2
公开(公告)日：2001-02-06
申请号：US09239344
申请日：1999-01-28
IPC分类号： H01L2362
CPC分类号： H01L27/0255 , H01L27/0288
摘要： The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.
摘要翻译： I / O电路的n沟道和p沟道驱动器晶体管是通过利用一对阱电阻保护的静电放电（ESD），其阻止ESD事件到达驱动器晶体管，并且形成指示ESD的二极管 事件到电路的电源轨或接地。
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公开(公告)号：US06184552B2
公开(公告)日：2001-02-06
申请号：US09118574
申请日：1998-07-17
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/11524
摘要： In a non-volatile memory cell that has a select transistor and a memory transistor, the substrate trenching that occurs when the gate of the select transistor and the stacked gate of the memory transistor are initially defined is eliminated by forming the gate of the select transistor and the stacked gate of the memory transistor to have substantially the same step height.
摘要翻译： 在具有选择晶体管和存储晶体管的非易失性存储单元中，通过形成选择晶体管的栅极来消除当选择晶体管的栅极和存储晶体管的堆叠栅极最初被限定时发生的衬底沟槽 并且存储晶体管的堆叠栅极具有基本上相同的台阶高度。
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公开(公告)号：US06180994B2
公开(公告)日：2001-01-30
申请号：US09234007
申请日：1999-01-19
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The array includes a plurality of spaced-apart bit lines which are formed in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word line includes a dielectric layer and a conductive layer.
摘要翻译： 通过一种降低阵列对屏蔽对准误差的灵敏度的方法形成侧壁接触的反熔丝阵列。 阵列包括形成在半导体材料中的多个间隔开的位线。 绝缘触点的行和列形成在半导体材料上，使得每个位线通过绝缘接触多次接触。 在每排触点中，每个触点具有暴露的侧壁。 在触点上形成多个字线，使得在一排暴露的侧壁中的每个暴露的侧壁上形成字线。 字线包括电介质层和导电层。
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