公开(公告)号：US06737335B2

公开(公告)日：2004-05-18

申请号：US10440806

申请日：2003-05-19

申请人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

发明人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

IPC分类号： H01L2176

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11541 ,  Y10S438/981

摘要： A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

摘要翻译： 浅沟槽隔离型半导体器件包括在第一区域和第二区域中形成的栅极绝缘层。 栅极绝缘层相对于第二区域中的栅极绝缘层的厚度在第一区域中具有更大的厚度。 在第一区域和第二区域中还形成浅沟槽隔离层，第一区域中的浅沟槽隔离层比第二区域中的浅沟槽隔离层更薄。

公开(公告)号：US6118696A

公开(公告)日：2000-09-12

申请号：US305239

申请日：1999-05-04

申请人： Jung-Dal Choi

发明人： Jung-Dal Choi

IPC分类号： H01L21/8247 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  H01L27/115 ,  G11C16/08 ,  G11C16/24 ,  G11C7/18

摘要： A memory cell array of a non-volatile semiconductor memory device includes unit strings grouped into first strings belonging to a first string group and second strings belonging to a second string group. Each unit string has a memory cells for storing data in a non-volatile state. Each first string is coupled between an associated bit line of a first bit line group and a first common source line whereas each second string is coupled between an associated bit line of a second bit line group and a second common source line. The bit lines and the common source lines are made of different conductive layers. In accordance with the invention, it is possible to achieve a less critical layout of sense amplifiers coupled to bit lines while easily performing a photolithography process as required in the manufacture of the memory device.

摘要翻译： 非易失性半导体存储器件的存储单元阵列包括分组为属于第一串组的第一串的单元串和属于第二串组的第二串。 每个单元串具有用于将数据存储在非易失性状态的存储单元。 每个第一串耦合在第一位线组的相关位线和第一公共源极线之间，而每个第二串耦合在第二位线组的相关位线和第二公共源极线之间。 位线和公共源极线由不同的导电层制成。 根据本发明，可以实现耦合到位线的感测放大器的不太重要的布局，同时容易地执行在制造存储器件中所需的光刻工艺。

公开(公告)号：US5936887A

公开(公告)日：1999-08-10

申请号：US910025

申请日：1997-08-12

申请人： Jung-Dal Choi ,  Dong-Jun Kim ,  Wang-Chul Shin ,  Jong-Han Kim

发明人： Jung-Dal Choi ,  Dong-Jun Kim ,  Wang-Chul Shin ,  Jong-Han Kim

IPC分类号： H01L21/8247 ,  G11C11/56 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C11/5621 ,  G11C16/0483 ,  H01L27/11521 ,  G11C16/24 ,  G11C2211/5649 ,  G11C7/18

摘要： A non-volatile memory device is disclosed in which a pair of two adjacent memory cell strings are commonly connected to one bit line and the memory cell strings are selectively driven to obtain a relatively wide pitch margin between two bit lines. The device has a conductive plate line which is located along each memory cell string or a pair of memory cell strings to drive memory cells thereof with a relatively low program voltage to a word line. The memory device comprises a plurality of memory cell strings which are arranged in parallel with one another and each of which extends in the same direction as a bit line 12, and a pair of two adjacent memory cell strings 11a and 11b are commonly connected to the bit line 12. The memory device also comprises a string selector for selecting either the first string 11a or the second string 11b in response to signals from string select lines SSL1 and SSL2, and a plurality of plate lines PLa or 21a and PLb or 21b which are respectively arranged on the first and second strings 11a and 11b. In the memory cell, if voltages having different levels are applied to the control gate of a memory cell of the string selected thus and the plate line, at least more than two coupling voltages are induced to a floating gate of a corresponding memory cell so that two bits of information can be stored in and read out of one memory cell. The memory device has a cell structure in which a pair of two adjacent memory cell strings are commonly connected to one bit line, so that margin width between two bit lines, i.e., a bit line pitch can be relatively widely obtained.

摘要翻译： 公开了一种非易失性存储器件，其中一对两个相邻的存储器单元串共同连接到一个位线，并且存储器单元串被选择性地驱动以在两个位线之间获得相对较宽的间距余量。 该装置具有沿着每个存储单元串或一对存储单元串定位的导电板线，以将具有相对低的编程电压的存储单元驱动到字线。 存储器件包括彼此并联布置的多个存储单元串，并且每个存储单元串沿与位线12相同的方向延伸，并且一对两个相邻的存储单元串11a和11b共同连接到 存储装置还包括用于响应于来自串选择线SSL1和SSL2的信号以及多个板线PLa或21a和PLb或21b而选择第一串11a或第二串11b的串选择器，其中 分别布置在第一和第二弦11a和11b上。 在存储单元中，如果将具有不同电平的电压施加到由此选择的串的存储单元的控制栅极和板线，则至少两个耦合电压被感应到相应存储单元的浮动栅极，使得 两位信息可以存储在一个存储单元中并从其中读出。 存储器件具有单元结构，其中一对两个相邻的存储单元串共同连接到一个位线，使得可以相对广泛地获得两个位线之间的裕度宽度，即位线间距。

公开(公告)号：US20140106518A1

公开(公告)日：2014-04-17

申请号：US14134457

申请日：2013-12-19

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L27/105

CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

公开(公告)号：US08546870B2

公开(公告)日：2013-10-01

申请号：US12622594

申请日：2009-11-20

申请人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Sung-Il Chang ,  Young-Woo Park ,  Jung-Dal Choi

发明人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Sung-Il Chang ,  Young-Woo Park ,  Jung-Dal Choi

IPC分类号： H01L29/792

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/4234

摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。 在第二电介质图案上提供第一导电图案。 具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

公开(公告)号：US08315102B2

公开(公告)日：2012-11-20

申请号：US13289689

申请日：2011-11-04

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08237199B2

公开(公告)日：2012-08-07

申请号：US12850677

申请日：2010-08-05

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Chang-Hyun Lee ,  Jang-Sik Lee ,  Vie-Na Kim

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Chang-Hyun Lee ,  Jang-Sik Lee ,  Vie-Na Kim

IPC分类号： H01L29/94

CPC分类号： G11C8/14 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.

摘要翻译： 电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于 与第一区域的顶表面不同的水平。 单元阵列还包括跨越第一区域的多个字线。 单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

公开(公告)号：US08217467B2

公开(公告)日：2012-07-10

申请号：US12984860

申请日：2011-01-05

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

摘要翻译： 在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。 半导体存储器件还包括在衬底上的器件隔离图案。 器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。 半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。 半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。 半导体存储器件还包括第三有源区中的第三源/漏区。 半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

公开(公告)号：US20120168852A1

公开(公告)日：2012-07-05

申请号：US13357350

申请日：2012-01-24

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

公开(公告)号：US08125015B2

公开(公告)日：2012-02-28

申请号：US12984630

申请日：2011-01-05

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/76

CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

摘要翻译： 描述了非易失性存储器件及其制造方法。 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 每个晶体管包括沟道区和源极/漏极区。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。