Motherboard having time delay circuit for delaying PSON signal
    91.
    发明授权
    Motherboard having time delay circuit for delaying PSON signal 有权
    主板具有用于延迟PSON信号的延时电路

    公开(公告)号:US08806234B2

    公开(公告)日:2014-08-12

    申请号:US13049909

    申请日:2011-03-17

    IPC分类号: G06F1/26

    CPC分类号: G06F1/24 G06F1/305

    摘要: A motherboard includes a motherboard power supply connector and a time delay circuit. The motherboard power supply connector connects a power supply unit. The motherboard power supply connector has a power supply on pin and a power good pin. The power good pin is configured for receiving a power good signal from the power supply unit. The time delay circuit has an input terminal and an output terminal. The input terminal is configured for receiving a power supply on signal. The output terminal is connected to the power supply on pin and is configured for sending the power supply on signal to the power supply on pin after a time delay determined by the time delay circuit.

    摘要翻译: 主板包括主板电源连接器和延时电路。 主板电源连接器连接电源单元。 主板电源连接器有一个引脚电源和一个电源良好的引脚。 电源良好引脚配置为从电源单元接收电源良好信号。 延时电路具有输入端和输出端。 输入端子被配置为接收电源接通信号。 输出端子连接到引脚上的电源,并配置为在由延时电路确定的时间延迟后,将电源接通信号发送到引脚上的电源。

    Buck converter
    94.
    发明授权
    Buck converter 失效
    降压转换器

    公开(公告)号:US08659281B2

    公开(公告)日:2014-02-25

    申请号:US13093209

    申请日:2011-04-25

    IPC分类号: H02M3/156

    摘要: A buck converter includes a first MOSFET and a second MOSFET connected in series, a PWM module coupled to gates of the first MOSFET and the second MOSFET, and a control unit being coupled to the input current acquired unit, the input voltage acquired unit, the output current acquired unit, the output voltage acquired unit and the PWM module respectively, wherein the control unit controls a switch frequency of the PWM module and acquires the input current, the input voltage, the output current and the output voltage from the input current acquired unit, the input voltage acquired unit, the output current acquired unit and the output voltage acquired unit respectively.

    摘要翻译: 降压转换器包括串联连接的第一MOSFET和第二MOSFET,连接到第一MOSFET和第二MOSFET的栅极的PWM模块,以及耦合到输入电流获取单元的控制单元,输入电压获取单元, 输出电流获取单元,输出电压获取单元和PWM模块,其中控制单元控制PWM模块的开关频率,并从获得的输入电流获取输入电流,输入电压,输出电流和输出电压 单位,输入电压获取单位,输出电流获取单位和输出电压采集单位。

    Driving voltage adjusting circuit capable of adjusting driving voltage via digital rheostat
    95.
    发明授权
    Driving voltage adjusting circuit capable of adjusting driving voltage via digital rheostat 失效
    驱动电压调节电路能够通过数字变阻器调节驱动电压

    公开(公告)号:US08643353B2

    公开(公告)日:2014-02-04

    申请号:US13053408

    申请日:2011-03-22

    IPC分类号: G05F1/575

    CPC分类号: G05F1/575

    摘要: A driving voltage adjusting circuit includes a digital rheostat, a control chip, a low dropout regulating circuit, and a driving circuit. The control chip is connected with the digital rheostat, and configured for adjusting the resistance of the digital rheostat. The low dropout regulating circuit is connected with the digital rheostat and outputs an output voltage according to the resistance of the digital rheostat. The driving circuit comprising a number of switch elements connected with each other and a driver configured for driving the switch elements, each of the switch elements comprising a first terminal, a second terminal, and a control terminal configured for controlling connection and disconnection of the first terminal and the second terminal; the first terminal and the second terminal connected with the control chip, the driver is connected with the low dropout regulating circuit and output an driving voltage to the control terminal.

    摘要翻译: 驱动电压调节电路包括数字变阻器,控制芯片,低压差调节电路和驱动电路。 控制芯片与数字变阻器连接,并配置用于调节数字变阻器的电阻。 低压差调节电路与数字变阻器相连,并根据数字变阻器的电阻输出一个输出电压。 所述驱动电路包括彼此连接的多个开关元件和被配置为驱动所述开关元件的驱动器,所述开关元件中的每一个包括第一端子,第二端子和控制端子,所述第一端子,第二端子和控制端子被配置为用于控制所述开关元件的连接和断开 终端和第二终端; 与控制芯片连接的第一端子和第二端子,驱动器与低压差调节电路连接,并向控制端子输出驱动电压。

    Buck converter
    96.
    发明授权
    Buck converter 失效
    降压转换器

    公开(公告)号:US08599580B2

    公开(公告)日:2013-12-03

    申请号:US13092217

    申请日:2011-04-22

    IPC分类号: H02M3/335

    摘要: A buck converter includes a first electrical switch and a second electrical switch connected in series, a PWM module coupled to the gate of the first electrical switch through a first adjustable resistance module and coupled to the gate of the second electrical switch through a second adjustable resistance module, a filter circuit coupled between the connecting node of the two different electrical switches and an output node, and a control module for adjusting values of the first adjustable resistance module and the second adjustable resistance module and acquiring a voltage value from the connecting node.

    摘要翻译: 降压转换器包括串联连接的第一电开关和第二电开关,PWM模块通过第一可调电阻模块耦合到第一电开关的栅极,并通过第二可调电阻耦合到第二电开关的栅极 模块,耦合在两个不同电气开关的连接节点和输出节点之间的滤波器电路,以及用于调整第一可调电阻模块和第二可调电阻模块的值并从连接节点获取电压值的控制模块。

    PLASMA PROCESSING APPARATUS
    97.
    发明申请
    PLASMA PROCESSING APPARATUS 审中-公开
    等离子体加工设备

    公开(公告)号:US20130256129A1

    公开(公告)日:2013-10-03

    申请号:US13876133

    申请日:2010-12-22

    IPC分类号: C23C14/35

    摘要: A plasma processing apparatus includes a chamber (20) and a target (25) above the chamber (20). The surface of the target (25) contacts the processing area of the chamber (20). The chamber (20) includes an insulating sub-chamber (21) and a first conductive sub-chamber (22), which are superposed. The first conductive sub-chamber (22) is provided under the insulating sub-chamber (21). The insulating sub-chamber (21) is made of insulating material, and the first conductive sub-chamber (22) is made of metal material. A Faraday shield component (10) which is made of metal material or insulating material electroplated with conductive coatings and includes at least one slit is provided in the insulating sub-chamber (21). An inductance coil (13) surrounds the exterior of the insulating sub-chamber (21). The problem about the wafer contamination due to particles formed on the surface of the coil during the sputtering process can be solved by using the plasma processing apparatus.

    摘要翻译: 等离子体处理装置包括在室(20)上方的室(20)和目标(25)。 靶(25)的表面与腔室(20)的处理区域接触。 所述腔室(20)包括叠置的绝缘子室(21)和第一导电子室(22)。 第一导电子室(22)设置在绝缘子室(21)的下方。 绝缘子室(21)由绝缘材料制成,第一导电子室(22)由金属材料制成。 在绝缘子室(21)中设置由金属材料制成的法拉第屏蔽部件(10)或电镀有导电涂层并且包括至少一个狭缝的绝缘材料。 电感线圈(13)围绕绝缘子室(21)的外部。 通过使用等离子体处理装置可以解决由于在溅射过程中在线圈表面上形成的颗粒导致的晶片污染的问题。

    Resistance determining system and method for circuit protection
    98.
    发明授权
    Resistance determining system and method for circuit protection 失效
    电阻确定系统和电路保护方法

    公开(公告)号:US08542473B2

    公开(公告)日:2013-09-24

    申请号:US13094754

    申请日:2011-04-26

    IPC分类号: H02H3/24

    CPC分类号: H02H3/006 H02H3/24

    摘要: A resistance determining system and method for a protection circuit, includes a resistance determining unit. The resistance determining unit interconnects a microcontroller and a digital resistor, where the microcontroller has first setting voltage corresponding to a first voltage threshold for activating the protection circuit, and the microcontroller is capable of receiving and converting a first external voltage input to the protection circuit to be a first converted voltage. The digital resistor includes a first variable resistor having two terminals connected to the respective first terminal and the second terminal. The microcontroller adjusts a resistance of the first variable resistor to be a first threshold resistance if the first converted voltage is substantially equal to the first voltage threshold, and the first resistance is determined to be substantially equal to the first threshold resistance.

    摘要翻译: 一种用于保护电路的电阻确定系统和方法,包括电阻确定单元。 电阻确定单元将微控制器和数字电阻相互连接,其中微控制器具有对应于用于启动保护电路的第一电压阈值的第一设定电压,并且微控制器能够接收和转换到保护电路的第一外部电压输入到 成为第一个转换电压。 数字电阻器包括具有连接到相应的第一端子和第二端子的两个端子的第一可变电阻器。 如果第一转换电压基本上等于第一电压阈值,则微控制器将第一可变电阻器的电阻调整为第一阈值电阻,并且确定第一电阻基本上等于第一阈值电阻。

    Measurement circuit for capacitor
    99.
    发明授权
    Measurement circuit for capacitor 失效
    电容测量电路

    公开(公告)号:US08456172B2

    公开(公告)日:2013-06-04

    申请号:US12981507

    申请日:2010-12-30

    IPC分类号: G01R31/12

    CPC分类号: G01R31/028 G01R31/025

    摘要: A measurement circuit includes a switch unit with a number of keys selectively pressed to output different resistance regulating signals. A resistance setting circuit receives the resistance regulating signals and connects different resistances to a voltage circuit and a current circuit. The voltage circuit outputs different voltages. The current voltage receives a voltage from the voltage circuit and outputs a current to a capacitor. A detecting circuit measures a temperature of the capacitor and outputs the temperature to the resistance setting circuit. The resistance setting circuit compares the received temperature with a preset temperature. If the received temperature is equal to or greater than the preset temperature, the resistance setting circuit outputs short-circuit information of the capacitor. If the received temperature is less than the preset temperature, the resistance setting circuit outputs normal information of the capacitor. A display unit displays the information of the capacitor.

    摘要翻译: 测量电路包括具有多个键的开关单元,其被选择性地按压以输出不同的电阻调节信号。 电阻设定电路接收电阻调节信号,并将不同的电阻连接到电压电路和电流电路。 电压电路输出不同的电压。 电流电压从电压电路接收电压并向电容器输出电流。 检测电路测量电容器的温度并将温度输出到电阻设定电路。 电阻设定电路将接收到的温度与预设温度进行比较。 如果接收到的温度等于或大于预设温度,则电阻设定电路输出电容器的短路信息。 如果接收到的温度低于预设温度,则电阻设定电路输出电容器的正常信息。 显示单元显示电容器的信息。

    Method and apparatus for detecting clock frequency deviation
    100.
    发明授权
    Method and apparatus for detecting clock frequency deviation 有权
    检测时钟频率偏差的方法和装置

    公开(公告)号:US08416901B2

    公开(公告)日:2013-04-09

    申请号:US12646671

    申请日:2009-12-23

    IPC分类号: H04L7/00

    CPC分类号: G01R23/02

    摘要: The embodiment of the present disclosure discloses a method and apparatus for detecting frequency deviation of a clock. The method includes: counting the clock to be detected to acquire current counting information; filtering the current counting information to acquire filtered data; and acquiring the frequency deviation of the clock to be detected from the filtered data. According to the embodiments of the present disclosure, the detection accuracy of frequency deviation is improved by filtering the counting information acquired by counting the clock to be detected, and appropriately increasing an amount of information after the filtering, so as to perceive the occurrence of any abnormal dithering, and avoid neglecting of any abnormal condition in periodic or aperiodic queries.

    摘要翻译: 本公开的实施例公开了一种用于检测时钟的频率偏差的方法和装置。 该方法包括:对要检测的时钟进行计数以获取当前计数信息; 过滤当前计数信息以获得过滤数据; 并从滤波后的数据中获取要检测的时钟的频率偏差。 根据本公开的实施例,通过对通过对要检测的时钟进行计数而获取的计数信息进行滤波,并适当地增加滤波后的信息量来提高频偏的检测精度,以便感知到任何 异常抖动,并避免在周期性或非周期性查询中忽略任何异常情况。