公开(公告)号：US20080097068A1

公开(公告)日：2008-04-24

申请号：US11660807

申请日：2005-10-11

申请人： Verena Thiede ,  Christian Bruchertseifer ,  Gerhard Mueller

发明人： Verena Thiede ,  Christian Bruchertseifer ,  Gerhard Mueller

IPC分类号： C08L75/04 ,  C08G18/10 ,  C08G18/42 ,  C08G18/76

CPC分类号： C08G18/4277 ,  C08G18/10 ,  C08G18/7671

摘要： The present invention relates to an isocyanate-terminated prepolymer composition obtained from reaction of a methylene diphenylisocyanate, comprising at least 25 weight percent of the 2,4′- isomer, with a polycaprolactone polyol; and to polyurethane or polyurea elastomers obtained from the said isocyanate-terminated prepolymer composition.

摘要翻译： 本发明涉及由包含至少25重量％的2,4'-异构体的亚甲基二苯基异氰酸酯与聚己内酯多元醇的反应获得的异氰酸酯封端的预聚物组合物; 以及由所述异氰酸酯封端的预聚物组合物获得的聚氨酯或聚脲弹性体。

公开(公告)号：US07187576B2

公开(公告)日：2007-03-06

申请号：US10925487

申请日：2004-08-25

申请人： Daniel Braun ,  Gerhard Mueller

发明人： Daniel Braun ,  Gerhard Mueller

IPC分类号： G11C11/00

CPC分类号： G11C11/5607 ,  G11C11/15 ,  G11C2211/5634

摘要： A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a MTJ. The MTJ includes a soft and two fixed magnetic layers with fixed field directions oriented in perpendicular directions. The soft magnetic layer is separated from the fixed layers by insulating layers preferably with different thicknesses, or with different material compositions. The resulting junction resistance can exhibit at least four distinct resistance values dependent on the magnetic orientation of the free magnetic layer. The cell is configured using a pattern with four lobes to store two bits, and eight lobes to store three bits. The resulting cell can be used to provide a fast, non-volatile magnetic random access memory (MRAM) with high density and no need to rewrite stored data after they are read, or as a fast galvanic isolator.

摘要翻译： 磁隧道结（MTJ）装置被配置为利用MTJ的可变电阻特性在单个单元中存储至少两位数据。 MTJ包括一个软和两个固定的磁性层，固定磁场方向定向在垂直方向。 软磁性层通过优选具有不同厚度或不同材料组成的绝缘层与固定层分离。 所得到的结电阻可以显示取决于自由磁性层的磁取向的至少四个不同的电阻值。 使用具有四个波瓣的模式来存储单元，以存储两个位，并且八个波瓣存储三个位。 所得到的单元可以用于提供高密度的快速，非易失性磁性随机存取存储器（MRAM），并且不需要在读取之后重写存储的数据，或者作为快速电流隔离器。

公开(公告)号：US07146471B2

公开(公告)日：2006-12-05

申请号：US10748333

申请日：2003-12-31

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

IPC分类号： G06F12/02

CPC分类号： G06F13/1694 ,  Y02D10/14

摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

摘要翻译： 公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。 示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。 当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。 通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

公开(公告)号：US07060529B2

公开(公告)日：2006-06-13

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/50 ,  H01L21/30

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US20060091476A1

公开(公告)日：2006-05-04

申请号：US11258367

申请日：2005-10-26

申请人： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

发明人： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

IPC分类号： H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/00

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76804 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

摘要翻译： 可以在图案化层中限定具有基本上小于可以光刻获得的特征尺寸的第一尺寸的开口的方法，包括将由不同于图案形成层的材料制成的牺牲层 图案化层上的预定层厚度。 之后，在牺牲层的表面上施加光致抗蚀剂层，并且在光致抗蚀剂层中光刻地限定具有第二尺寸的开口。 之后，以取决于牺牲层的层厚度以及第一和第二尺寸的方式设置蚀刻角度，并且以蚀刻角度设置蚀刻牺牲层。 之后，蚀刻图形层，去除牺牲层，并将填充材料引入图案化层中产生的开口中。

公开(公告)号：US20050001298A1

公开(公告)日：2005-01-06

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/8242 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18 ,  H01L27/105 ,  H01L23/544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06758237B2

公开(公告)日：2004-07-06

申请号：US10319810

申请日：2002-12-16

申请人： Wolfgang Sichler ,  Matthias Fastanz ,  Fabian Maier ,  Gerhard Mueller

发明人： Wolfgang Sichler ,  Matthias Fastanz ,  Fabian Maier ,  Gerhard Mueller

IPC分类号： B23B4108

CPC分类号： F16L47/34 ,  Y10T137/6123 ,  Y10T408/5628 ,  Y10T408/896 ,  Y10T408/907

摘要： A tapping valve having a housing which can be electrically welded to a pipe and which includes a connection piece (2) with a drill (24) therein for drilling the pipe. The connection piece has an inner surface (34). The drill or a bushing (70) in which the drill can be moved axially by a threaded connection (74, 76; 80, 82) is provided with an external thread which engages the inner surface of the connection piece. Inner surface (34) is constructed such that it is initially cylindrical adjacent the external thread (32) and an inner thread can be formed in the inner surface (34) using the external thread (32) by rotating the drill (24) or the thread (70) in an axially forward direction (30). The tapping valve is easy to manufacture and yet offers a high degree of functional reliability.

摘要翻译： 一种排水阀，其具有壳体，该壳体可以电焊接到管道上，并且包括具有用于钻出管道的钻头（24）的连接件（2）。 连接件具有内表面（34）。 钻头或其中钻头可以通过螺纹连接（74,76,80,82）轴向移动的衬套（70）设置有与连接件的内表面接合的外螺纹。 内表面（34）被构造成使得其最初是与外螺纹（32）相邻的圆柱形，并且可以使用外螺纹（32）通过旋转钻（24）或内螺纹（32）在内表面（34）中形成内螺纹 螺纹（70）沿轴向向前方向（30）。 排水阀易于制造，并提供高度的功能可靠性。

公开(公告)号：US06736001B1

公开(公告)日：2004-05-18

申请号：US09958957

申请日：2002-01-16

申请人： Gerhard Mueller ,  Thomas Becker

发明人： Gerhard Mueller ,  Thomas Becker

IPC分类号： G01N2712

CPC分类号： G01N27/12 ,  G01N33/0009

摘要： A semiconductor gas sensor, for example for measuring CO, NOx, O3, etc., exhibits a heatable sensor element for measuring gas concentrations, and a housing in whose interior the sensor element is disposed. The housing has a first opening, which connects the interior to the exterior. The housing has one or more second openings, which lie deeper than the first opening so that a gas stream is driven by means of convection from the second opening to the first opening. The semiconductor gas sensor can be made of silicon by means of micro engineering.

摘要翻译： 例如用于测量CO，NO x，O 3等的半导体气体传感器表现出用于测量气体浓度的可加热传感器元件，以及在其内部设置传感器元件的壳体。 壳体具有将内部连接到外部的第一开口。 壳体具有一个或多个第二开口，其比第一开口更深，使得气流通过从第二开口到第一开口的对流来驱动。 半导体气体传感器可以通过微型工程制成硅。

公开(公告)号：US06529054B1

公开(公告)日：2003-03-04

申请号：US09425329

申请日：1999-10-22

申请人： David Russell Hanson ,  Gerhard Mueller

发明人： David Russell Hanson ,  Gerhard Mueller

IPC分类号： H03L716

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/107 ,  H04J3/0685 ,  H04L7/0008

摘要： A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing signals and to serially output on the first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of the plurality of timing signals. The first high frequency timing pulse stream has a timing pulse stream frequency that is higher than a timing input frequency associated with one of the first plurality of timing signals. The synchronized data capture circuit also includes first plurality of data driver circuits coupled to receive the first plurality of data signals and the plurality of timing signals. The first plurality of data driver circuits are configured to serially output, as a first high frequency data stream, first data pulses responsive to the timing pulses of the plurality of timing signals and data pulses of the first plurality of data signal. The first high frequency data stream has a data stream frequency that is higher than a data input frequency associated with one of the first plurality of data signals. The synchronized data capture circuit further includes a first data clocking circuit coupled to receive the first high frequency data stream and the first high frequency timing pulse stream to synchronize capture of data in the first high frequency data stream using the first high frequency timing pulse stream to output the synchronized data capture signal, wherein the synchronized data capture signal has a data output frequency that is higher than the timing input frequency and the data input frequency.

摘要翻译： 一种同步数据捕获电路，被配置为将第一多个数据信号中的数据的采集与第一多个定时信号同步，以输出同步的数据捕获信号。 同步数据捕获电路包括具有第一定时发生器输出的定时发生器。 定时器发生器被耦合以接收第一多个定时信号，并且在第一定时器发生器输出上串行地输出作为第一高频定时脉冲流的响应于多个定时信号的定时脉冲的第一定时脉冲。 第一高频定时脉冲流具有比与第一多个定时信号之一相关联的定时输入频率高的定时脉冲流频率。 同步数据捕获电路还包括耦合以接收第一多个数据信号和多个定时信号的第一多个数据驱动器电路。 第一多个数据驱动器电路被配置为响应于多个定时信号的定时脉冲和第一多个数据信号的数据脉冲串行地输出第一数据脉冲作为第一高频数据流。 第一高频数据流具有比与第一多个数据信号之一相关联的数据输入频率高的数据流频率。 同步数据捕获电路还包括第一数据时钟电路，其耦合以接收第一高频数据流和第一高频定时脉冲流，以使用第一高频定时脉冲流将第一高频数据流中的数据捕获同步到 输出同步数据捕获信号，其中同步数据捕获信号具有高于定时输入频率和数据输入频率的数据输出频率。

公开(公告)号：US6081479A

公开(公告)日：2000-06-27

申请号：US333539

申请日：1999-06-15

申请人： Brian Ji ,  Toshiaki Kirihata ,  Gerhard Mueller ,  David Hanson

发明人： Brian Ji ,  Toshiaki Kirihata ,  Gerhard Mueller ,  David Hanson

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1039

摘要： A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

摘要翻译： 根据本发明的半导体存储器包括包括多个分层级的数据路径，每个级包括与其他级不同的位数据速率。 至少两个预取电路设置在各级之间。 至少两个预取电路包括用于接收数据位并存储数据位的至少两个锁存器，直到层级中的下一级能够接收数据位。 所述至少两个预取电路耦合在级之间，使得级之间每级的总体数据速率基本相等。 控制信号控制至少两个锁存器，使得预取电路保持级之间的总体数据速率。