公开(公告)号：US09190520B2

公开(公告)日：2015-11-17

申请号：US14481146

申请日：2014-09-09

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Dechao Guo ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Kern Rim ,  Huiling Shang

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

Abstract translation: 翅片结构包括可选的掺杂阱，一次性单晶半导体材料部分和形成在衬底上的顶部半导体部分。 形成跨越翅片结构的一次性栅极结构，并且去除翅片结构的端部以形成端部空腔。 掺杂的半导体材料部分形成在一次性单晶半导体材料部分的堆叠的侧部和包括顶部半导体部分的沟道区域上。 一次性单晶半导体材料部分可以在移除一次性栅极结构之后或在堆叠形成之后用介电材料部分代替。 栅极腔填充有栅极电介质和栅电极。 沟道区域被掺杂的半导体材料部分应力，并且通过电介质材料部分与衬底电隔离。

公开(公告)号：US20150206885A1

公开(公告)日：2015-07-23

申请号：US14159030

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Herbert L. Ho ,  Ali Khakifirooz ,  Babar A. Khan ,  Shom Ponoth ,  Kern Rim ,  Kehan Tian ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L27/10879 ,  H01L21/283 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/945

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Abstract translation: 可以在半导体鳍片的纵向侧壁之间形成沟槽电容器，并且在半导体鳍片中形成存取晶体管的源极和漏极区域。 在相邻的一对半导体鳍片的端壁之间形成虚拟栅极结构，并且限制通过选择性外延形成的凸起的源极和漏极区域的横向范围。 虚拟栅极结构防止相邻半导体鳍片之间的电短路。 可以在栅极结构和虚拟栅极结构周围形成栅极间隔物。 虚拟栅极结构可以用虚拟替代栅极结构或介电材料部分代替，或者可以保持相同而不取代任何材料。 虚拟栅极结构可以由至少一种电介质材料组成，或者可以包括电浮动的导电材料部分。

公开(公告)号：US20140377924A1

公开(公告)日：2014-12-25

申请号：US14481146

申请日：2014-09-09

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Dechao Guo ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Kern Rim ,  Huiling Shang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.