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公开(公告)号：US10957603B2
公开(公告)日：2021-03-23
申请号：US16438573
申请日：2019-06-12
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/8238
摘要： A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.
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公开(公告)号：US20200098893A1
公开(公告)日：2020-03-26
申请号：US16684115
申请日：2019-11-14
发明人： Michael A. Guillorn , Terence B. Hook , Robert R. Robison , Reinaldo A. Vega , Rajasekhar Venigalla
IPC分类号： H01L29/66 , B82Y10/00 , H01L29/06 , H01L29/775 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/28 , H01L29/49
摘要： A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
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公开(公告)号：US10340340B2
公开(公告)日：2019-07-02
申请号：US15298737
申请日：2016-10-20
发明人： Ruqiang Bao , Michael A. Guillorn , Terence B. Hook , Nicolas J. Loubet , Robert R. Robison , Reinaldo A. Vega , Tenko Yamashita
IPC分类号： H01L29/06 , H01L29/423 , H01L29/08 , H01L29/10 , H01L29/786 , B82Y10/00 , H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/775
摘要： Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.
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公开(公告)号：US10177154B2
公开(公告)日：2019-01-08
申请号：US15691182
申请日：2017-08-30
发明人： Michael V. Aquilino , Veeraraghavan S. Basker , Kangguo Cheng , Gregory Costrini , Ali Khakifirooz , Byeong Y. Kim , William L. Nicoll , Ravikumar Ramachandran , Reinaldo A. Vega , Hanfei Wang , Xinhui Wang
IPC分类号： H01L29/94 , H01L27/108 , H01L27/12 , H01L27/08
摘要： After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
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公开(公告)号：US10109535B2
公开(公告)日：2018-10-23
申请号：US15345604
申请日：2016-11-08
IPC分类号： H01L21/8238 , H01L29/66 , H01L21/28 , H01L29/786 , H01L29/06 , H01L29/423 , H01L29/49 , H01L27/092
摘要： A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.
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公开(公告)号：US10032885B2
公开(公告)日：2018-07-24
申请号：US15180499
申请日：2016-06-13
发明人： Gauri Karve , Robert R. Robison , Reinaldo A. Vega
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/78 , H01L27/092 , H01L21/225 , H01L29/36 , H01L21/8234 , H01L21/8238 , H01L21/265
摘要： A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.
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公开(公告)号：US20170365606A1
公开(公告)日：2017-12-21
申请号：US15691182
申请日：2017-08-30
发明人： Michael V. Aquilino , Veeraraghavan S. Basker , Kangguo Cheng , Gregory Costrini , Ali Khakifirooz , Byeong Y. Kim , William L. Nicoll , Ravikumar Ramachandran , Reinaldo A. Vega , Hanfei Wang , Xinhui Wang
IPC分类号： H01L27/108 , H01L27/12
CPC分类号： H01L27/1087 , H01L27/0817 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/10879 , H01L27/1203
摘要： After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
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8.发明申请公开(公告)号：US20170222021A1
公开(公告)日：2017-08-03
申请号：US15345604
申请日：2016-11-08
IPC分类号： H01L29/66 , H01L21/28 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49 , H01L21/8238 , H01L29/786
CPC分类号： H01L29/78642 , H01L21/28088 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L21/823885 , H01L21/845 , H01L27/0886 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/41741 , H01L29/41791 , H01L29/42356 , H01L29/42392 , H01L29/4966 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/785 , H01L29/7855 , H01L29/78618 , H01L29/78648 , H01L29/78696 , H01L2029/42388 , H01L2924/13067
摘要： A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.
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公开(公告)号：US20170178974A1
公开(公告)日：2017-06-22
申请号：US15148110
申请日：2016-05-06
IPC分类号： H01L21/8238 , H01L29/786 , H01L29/423 , H01L27/092 , H01L29/06
CPC分类号： H01L21/82385 , H01L21/02263 , H01L21/26566 , H01L21/32 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L21/823885 , H01L27/092 , H01L27/0922 , H01L29/0653 , H01L29/42392 , H01L29/4966 , H01L29/78618 , H01L29/78642 , H01L29/78696 , H01L2029/42388
摘要： A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.
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公开(公告)号：US09679993B2
公开(公告)日：2017-06-13
申请号：US15179699
申请日：2016-06-10
IPC分类号： H01L21/00 , H01L21/84 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/265 , H01L21/311 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/417 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02274 , H01L21/26533 , H01L21/26566 , H01L21/26586 , H01L21/31111 , H01L21/762 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823481 , H01L21/845 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/41791 , H01L29/7848 , H01L29/785
摘要： After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.
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