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公开(公告)号：US09741722B2
公开(公告)日：2017-08-22
申请号：US14874389
申请日：2015-10-03
发明人： John E. Barth, Jr. , Kangguo Cheng , Bruce B. Doris , Herbert L. Ho , Ali Khakifirooz , Babar A. Khan , Shom Ponoth , Kern Rim , Kehan Tian , Reinaldo A. Vega
IPC分类号： H01L21/283 , H01L21/762 , H01L27/108 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/78 , H01L29/94
CPC分类号： H01L27/10879 , H01L21/283 , H01L21/76224 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L29/0653 , H01L29/41783 , H01L29/41791 , H01L29/66181 , H01L29/6681 , H01L29/785 , H01L29/945
摘要： Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
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公开(公告)号：US20160027789A1
公开(公告)日：2016-01-28
申请号：US14874389
申请日：2015-10-03
发明人： John E. Barth, JR. , Kangguo Cheng , Bruce B. Doris , Herbert L. Ho , Ali Khakifirooz , Babar A. Khan , Shom Ponoth , Kern Rim , Kehan Tian , Reinaldo A. Vega
IPC分类号： H01L27/108 , H01L29/417 , H01L21/762 , H01L29/06 , H01L21/283 , H01L29/66
CPC分类号： H01L27/10879 , H01L21/283 , H01L21/76224 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L29/0653 , H01L29/41783 , H01L29/41791 , H01L29/66181 , H01L29/6681 , H01L29/785 , H01L29/945
摘要： Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
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3.发明授权公开(公告)号：US09117051B2
公开(公告)日：2015-08-25
申请号：US14059093
申请日：2013-10-21
发明人： Chieh-yu Lin , Kehan Tian , Sanghoon Baek
IPC分类号： G06F17/50 , H01L21/033 , H01L21/8234
CPC分类号： G06F17/5072 , H01L21/32139 , H01L21/823475 , H01L27/0207
摘要： A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.
摘要翻译： 设计布局包括一组表示半导体有源区域的有源区域级设计形状，以及一组表示栅极线跨越半导体有源区域的门级设计形状。 门级设计形状的集合包括连接两个门级设计形状的子分辨率辅助特征（SRAF），并且在使用光刻方法打印时物理地表现为两条栅极线之间的间隙。 可以使用包括具有突出水龙头的切割级设计形状的切割掩模来切割靠近半导体有源区域的栅极线的边缘。 突出的抽头允许可靠地去除栅极线的端部，并且防止由不想要的残留栅极结构破坏升高的源极和漏极区域。
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4.发明申请公开(公告)号：US20150111367A1
公开(公告)日：2015-04-23
申请号：US14059093
申请日：2013-10-21
发明人： Chieh-yu Lin , Kehan Tian , Sanghoon Baek
IPC分类号： G06F17/50 , H01L21/8234 , H01L21/033
CPC分类号： G06F17/5072 , H01L21/32139 , H01L21/823475 , H01L27/0207
摘要： A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.
摘要翻译： 设计布局包括一组表示半导体有源区域的有源区域级设计形状，以及一组表示栅极线跨越半导体有源区域的门级设计形状。 门级设计形状的集合包括连接两个门级设计形状的子分辨率辅助特征（SRAF），并且在使用光刻方法打印时物理地表现为两条栅极线之间的间隙。 可以使用包括具有突出水龙头的切割级设计形状的切割掩模来切割靠近半导体有源区域的栅极线的边缘。 突出的抽头允许可靠地去除栅极线的端部，并且防止由不想要的残留栅极结构破坏升高的源极和漏极区域。
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公开(公告)号：US11036126B2
公开(公告)日：2021-06-15
申请号：US16441911
申请日：2019-06-14
发明人： Chieh-Yu Lin , Dongbing Shao , Kehan Tian , Zheng Xu
IPC分类号： G06F30/33 , G03F1/36 , G03F1/70 , G03F1/38 , G06F30/20 , G06F30/398 , G06F119/18
摘要： Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
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公开(公告)号：US09651856B2
公开(公告)日：2017-05-16
申请号：US14985049
申请日：2015-12-30
CPC分类号： G03F1/36 , G03F7/70125 , G03F7/70308 , G03F7/70441 , G03F7/705 , G03F7/70516 , G06F17/5072
摘要： Methods and systems for determining a source shape, a mask shape and a target shape for a lithography process are disclosed. One such method includes receiving source, mask and target constraints and formulating an optimization problem that is based on the source, mask and target constraints and incorporates contour-based assessments for the target shape that are based on physical design quality of a circuit. Further, the optimization problem is solved by integrating over process condition variations to simultaneously determine the source shape, the mask shape and the target shape. In addition, the determined source shape and mask shape are output.
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7.发明申请公开(公告)号：US20160103389A1
公开(公告)日：2016-04-14
申请号：US14892987
申请日：2014-05-09
CPC分类号： G03F1/36 , G03F1/144 , G03F1/70 , G03F7/70433 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06F17/5072
摘要： A system and method for optimizing (designing) a mask pattern, in which SMO and OPC are collaboratively used to exert a sufficient collaborative effect or are appropriately used in different manners. The method for designing a source and a mask for lithography includes a step (S1) of selecting a set of patterns; a step of performing source mask optimization (SMO) using the set of patterns, under an optical proximity correction (OPC) restriction rule which is used for selectively restricting shifting of an edge position of a polygon when OPC is applied to the set of patterns; and a step (S3, S4) of determining a layout of the mask for lithography, by applying OPC to all patterns constituting the mask for lithography using the source optimized through the SMO.
摘要翻译： 一种用于优化（设计）掩模图案的系统和方法，其中协同使用SMO和OPC来发挥足够的协作效果或以不同的方式适当地使用。 用于设计用于光刻的源和掩模的方法包括：选择一组图案的步骤（S1）; 在OPC接口校正（OPC）限制规则下，使用该组图案执行源掩模优化（SMO）的步骤，该OPC限制规则用于当OPC应用于该组图案时用于选择性地限制多边形的边缘位置的移位; 以及通过使用通过SMO优化的源来对构成光刻掩模的所有图案应用OPC来确定用于光刻的掩模的布局的步骤（S3，S4）。
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8.发明授权Source, target and mask optimization by incorporating countour based assessments and integration over process variations 有权来源，目标和面具优化，包括基于countour的评估和整合过程变化公开(公告)号：US09250535B2
公开(公告)日：2016-02-02
申请号：US13837435
申请日：2013-03-15
CPC分类号： G03F1/36 , G03F7/70125 , G03F7/70308 , G03F7/70441 , G03F7/705 , G03F7/70516 , G06F17/5072
摘要： Methods and systems for determining a source shape, a mask shape and a target shape for a lithography process are disclosed. One such method includes receiving source, mask and target constraints and formulating an optimization problem that is based on the source, mask and target constraints and incorporates contour-based assessments for the target shape that are based on physical design quality of a circuit. Further, the optimization problem is solved by integrating over process condition variations to simultaneously determine the source shape, the mask shape and the target shape. In addition, the determined source shape and mask shape are output.
摘要翻译： 公开了用于确定光刻工艺的源形状，掩模形状和目标形状的方法和系统。 一种这样的方法包括接收源，掩码和目标约束并且制定基于源，掩码和目标约束的优化问题，并且基于基于电路的物理设计质量的目标形状的基于轮廓的评估。 此外，通过整合过程条件变化来同时确定源形状，掩模形状和目标形状来解决优化问题。 此外，输出确定的源形状和掩模形状。
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公开(公告)号：US20150206885A1
公开(公告)日：2015-07-23
申请号：US14159030
申请日：2014-01-20
发明人： John E. Barth, Jr. , Kangguo Cheng , Bruce B. Doris , Herbert L. Ho , Ali Khakifirooz , Babar A. Khan , Shom Ponoth , Kern Rim , Kehan Tian , Reinaldo A. Vega
IPC分类号： H01L27/108 , H01L29/06 , H01L29/417 , H01L29/66
CPC分类号： H01L27/10879 , H01L21/283 , H01L21/76224 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L29/0653 , H01L29/41783 , H01L29/41791 , H01L29/66181 , H01L29/6681 , H01L29/785 , H01L29/945
摘要： Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
摘要翻译： 可以在半导体鳍片的纵向侧壁之间形成沟槽电容器，并且在半导体鳍片中形成存取晶体管的源极和漏极区域。 在相邻的一对半导体鳍片的端壁之间形成虚拟栅极结构，并且限制通过选择性外延形成的凸起的源极和漏极区域的横向范围。 虚拟栅极结构防止相邻半导体鳍片之间的电短路。 可以在栅极结构和虚拟栅极结构周围形成栅极间隔物。 虚拟栅极结构可以用虚拟替代栅极结构或介电材料部分代替，或者可以保持相同而不取代任何材料。 虚拟栅极结构可以由至少一种电介质材料组成，或者可以包括电浮动的导电材料部分。
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公开(公告)号：US08959462B2
公开(公告)日：2015-02-17
申请号：US13795513
申请日：2013-03-12
CPC分类号： G03F1/70
摘要： A method, an article of manufacture, and a system for designing a mask. The method for designing a mask is implemented by a computer device having a memory, a processor device communicatively coupled to the memory, and a module configured to carry out the method including the steps of: generating an optical domain representation from a design pattern and an imaging light; and optimizing the optical domain representation under a constraint that values of negative excursions at predetermined evaluation points must be greater than or equal to predetermined negative threshold values assigned to the predetermined evaluation points; where: the optical domain representation is a variable representation of a wavefront; the imaging light is light that is transmitted through the mask; the negative excursions are in an object domain representation of the optical domain representation; and the predetermined evaluation points are in the object domain representation.
摘要翻译： 一种方法，制品和用于设计面罩的系统。 用于设计掩模的方法由具有存储器的计算机设备，通信地耦合到存储器的处理器设备和被配置为执行该方法的模块实现，该计算机设备包括以下步骤：从设计模式生成光学域表示 成像光; 并且在预定评估点处的负偏移值必须大于或等于分配给预定评估点的预定负阈值的约束下优化光域表示; 其中：光域表示是波前的可变表示; 成像光是通过掩模透射的光; 负偏移在光域表示的对象域表示中; 并且预定的评估点在对象域表示中。
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