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公开(公告)号：US10381338B2
公开(公告)日：2019-08-13
申请号：US15604090
申请日：2017-05-24
IPC分类号： H01L27/02 , H01L23/522
摘要： A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.
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公开(公告)号：US20180211947A1
公开(公告)日：2018-07-26
申请号：US15412608
申请日：2017-01-23
摘要： A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
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公开(公告)号：US20140252413A1
公开(公告)日：2014-09-11
申请号：US13792291
申请日：2013-03-11
发明人： Henry K. Utomo , Kangguo Cheng , Ramachandra Divakaruni , Myung-Hee Na , Ravikumar Ramachandran , Huiling Shang
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/66795
摘要： A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.
摘要翻译： 在包括硅的半导体衬底上形成第一硅锗合金层。 在第一硅 - 锗合金层的第一区域上形成第一硅层和第二硅 - 锗合金层的堆叠，并且在第一硅 - 锗合金层的第二区域上形成比第一硅层厚的第二硅层 硅锗合金层。 在第一区域中形成至少一个第一半导体鳍片，并且在第二区域中形成至少一个第二半导体鳍片。 去除第一硅层的剩余部分以在第一区域中提供至少一个硅 - 锗合金翅片，而在第二区域中提供至少一个硅片。 鳍状场效应晶体管可以形成在至少一个硅 - 锗合金翅片和至少一个硅片上。
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公开(公告)号：US08648647B2
公开(公告)日：2014-02-11
申请号：US13922854
申请日：2013-06-20
发明人： Myung-Hee Na , Edward J. Nowak
CPC分类号： G01R31/2601 , G01R31/2621
摘要： A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.
摘要翻译： 半导体包括：第一场效应晶体管（FET）; 以及与第一FET极性相似的第二FET，其中第一FET的主体电耦合到第二FET的主体，并且第一FET的源极电耦合到第二FET的源极，使得 第二FET的体电压控制第一FET的体电压。
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公开(公告)号：US10892331B2
公开(公告)日：2021-01-12
申请号：US16431866
申请日：2019-06-05
发明人： Tenko Yamashita , Myung-Hee Na
IPC分类号： H01L29/423 , H01L29/78 , H01L29/10 , H01L21/84 , H01L29/06 , H01L29/775 , H01L21/8238 , H01L29/66
摘要： Techniques are provided to fabricate semiconductor integrated circuit devices which include complementary metal-oxide-semiconductor gate-all-around field-effect transistor devices (e.g., nanosheet field-effect transistor devices), wherein the channel orientation layout of N-type and P-type field-effect transistor devices are independently configured to provide enhanced carrier mobility in the channel layers of the different type field-effect transistor devices.
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6.发明授权公开(公告)号：US10833267B2
公开(公告)日：2020-11-10
申请号：US16172643
申请日：2018-10-26
摘要： A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.
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公开(公告)号：US10803933B2
公开(公告)日：2020-10-13
申请号：US16107129
申请日：2018-08-21
摘要： A method of forming a self-aligned phase change memory element is provided. A bottom electrode is formed on a landing pad of a phase change memory element. A layer of dielectric material over the bottom electrode and a via etched through the dielectric material to expose the bottom electrode. The via is lined with a GST phase change layer that is etched back from the top surface of the dielectric layer. The via is then filled with a nitride fill, at least of portion of which is etched back from the top surface of the dielectric layer. A top electrode metal is then deposited at the top of the via, wherein the top electrode material is coupled to the phase change material and nitride fill material.
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公开(公告)号：US20200066337A1
公开(公告)日：2020-02-27
申请号：US16107129
申请日：2018-08-21
摘要： A method of forming a self-aligned phase change memory element is provided. A bottom electrode is formed on a landing pad of a phase change memory element. A layer of dielectric material over the bottom electrode and a via etched through the dielectric material to expose the bottom electrode. The via is lined with a GST phase change layer that is etched back from the top surface of the dielectric layer. The via is then filled with a nitride fill, at least of portion of which is etched back from the top surface of the dielectric layer. A top electrode metal is then deposited at the top of the via, wherein the top electrode material is coupled to the phase change material and nitride fill material.
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公开(公告)号：US10424576B2
公开(公告)日：2019-09-24
申请号：US15802956
申请日：2017-11-03
IPC分类号： G06F17/50 , H01L27/02 , H01L27/118
摘要： A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
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公开(公告)号：US20190189195A1
公开(公告)日：2019-06-20
申请号：US15849367
申请日：2017-12-20
发明人： Myung-Hee Na , Robert Wong , Jens Haetty , Sean Burns
IPC分类号： G11C11/412 , H01L27/11 , H01L27/118 , H01L27/088 , G11C11/419
CPC分类号： G11C11/412 , G11C11/419 , H01L27/0886 , H01L27/1108 , H01L27/11807 , H01L2027/11812
摘要： Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.
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