公开(公告)号：US10192781B2

公开(公告)日：2019-01-29

申请号：US15055451

申请日：2016-02-26

Applicant: International Business Machines Corporation

Inventor： Satya V. Nitta ,  Shom Ponoth

IPC: H01L21/4763 ,  H01L21/768 ,  G01H11/06 ,  G01H3/00 ,  G01H11/00 ,  H01L21/311 ,  G01H11/02

Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

公开(公告)号：US09673087B2

公开(公告)日：2017-06-06

申请号：US14846801

申请日：2015-09-06

Applicant: International Business Machines Corporation

Inventor： Satya V. Nitta ,  Shom Ponoth

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

公开(公告)号：US09508587B2

公开(公告)日：2016-11-29

申请号：US15041082

申请日：2016-02-11

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Shom Ponoth ,  Theodorus Standaert ,  Tenko Yamashita

IPC: H01L21/027 ,  H01L21/762 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3115 ,  H01L21/266 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/785

Abstract: Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials.

公开(公告)号：US09502292B2

公开(公告)日：2016-11-22

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/20 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09406548B2

公开(公告)日：2016-08-02

申请号：US14922224

申请日：2015-10-26

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Shom Ponoth ,  Theodorus Standaert ,  Tenko Yamashita

IPC: H01L21/027 ,  H01L21/762 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3115 ,  H01L21/266 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/785

Abstract: Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials.

公开(公告)号：US20160204064A1

公开(公告)日：2016-07-14

申请号：US15077157

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/525

CPC classification number: H01L21/76877 ,  H01L21/76814 ,  H01L23/5256 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

公开(公告)号：US09252242B2

公开(公告)日：2016-02-02

申请号：US13849694

申请日：2013-03-25

Applicant: International Business Machines Corporation

Inventor： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Junjun Li ,  Balasubramanian Pranatharthi Haran ,  Shom Ponoth ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/861 ,  H01L29/40 ,  H01L29/423 ,  H01L27/02 ,  H01L23/367 ,  H01L23/373 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L23/367 ,  H01L23/3738 ,  H01L27/0255 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/402 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/6609 ,  H01L29/66742 ,  H01L29/861 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.

Abstract translation: 提供用于集成电路的二极管和电阻。 深沟槽（DT）集成到二极管和电阻器中，用于热传导。 深沟槽促进热从绝缘体上半导体衬底传导到体衬底。 半导体散热片可形成为与深沟槽对齐。

公开(公告)号：US20160013269A1

公开(公告)日：2016-01-14

申请号：US14861207

申请日：2015-09-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian Pranatharthiharan ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

Abstract translation: 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

公开(公告)号：US09202749B2

公开(公告)日：2015-12-01

申请号：US14174089

申请日：2014-02-06

Applicant: International Business Machines Corporation

Inventor： Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/495 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76843 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897

Abstract: Methods for achieving advanced patterning of an interconnect dielectric material layer are provided in which the dimension, i.e., width, of an opening that is formed into a metallic hard mask layer is shrunk prior to extending the opening into the interconnect dielectric material layer. The shrinking of the dimension of the opening that is formed into the metallic hard mask layer can be achieved in the present application by forming at least a metallic hard mask spacer portion on a sidewall surface of each patterned metallic hard mask layer. The aforementioned basic principle can be applied to forming a line opening, a via opening and/or a combined via and line opening within an interconnect dielectric material layer, wherein each of the openings (line, via and/or via and line) has a reduced dimension as compared to that obtainable utilizing conventional lithography.

Abstract translation: 提供了用于实现互连电介质材料层的先进图案化的方法，其中形成金属硬掩模层的开口的尺寸，即宽度在将开口延伸到互连电介质材料层之前收缩。 通过在每个图案化的金属硬掩模层的侧壁表面上形成至少金属硬掩模间隔部分，可以在本申请中实现形成金属硬掩模层的开口尺寸的缩小。 上述基本原理可以应用于在互连电介质材料层内形成线路开口，通孔开口和/或组合的通孔和线路开口，其中开口（线路，通路和/或通孔和线路）中的每一个具有 与使用常规光刻可获得的尺寸相比，尺寸减小。

公开(公告)号：US20150340288A1

公开(公告)日：2015-11-26

申请号：US14529825

申请日：2014-10-31

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L27/10826 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

Abstract translation: 公开了一种改进的finFET和使用无硅无工艺流程的制造方法。 氮化物间隔件在形成用于无硅无机（SON）工艺的翅片下方的空腔的形成期间保护翅片侧面。 可流动氧化物填充空腔以在翅片下形成绝缘介电层。