公开(公告)号：US07765351B2

公开(公告)日：2010-07-27

申请号：US11684687

申请日：2007-03-12

申请人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

发明人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F9/526 ,  G06F9/544 ,  G06F15/167

摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。

公开(公告)号：US20090307637A1

公开(公告)日：2009-12-10

申请号：US12135250

申请日：2008-06-09

申请人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

发明人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/72

摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.

摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。

公开(公告)号：US20090239313A1

公开(公告)日：2009-09-24

申请号：US12343686

申请日：2008-12-24

申请人： Theodoros Anemikos ,  Ezra D.B. Hall ,  Sebastian T. Ventrone

发明人： Theodoros Anemikos ,  Ezra D.B. Hall ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  H01L21/66

CPC分类号： G06F17/5045 ,  G01R31/2884 ,  G01R31/3025 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

摘要翻译： 公开了设计和制造系统以及相关方法的实施例，其允许在晶片制造期间进行设计分析和插入过程内监控电路。 这些实施例使用预定义的内部过程监视电路库和将不同监控电路与不同IC芯片组件链接的互相关表。 具体地，这些实施例分析集成电路芯片设计数据以识别设计到芯片中的部件。 然后，从库中选择一个或多个进程内监控电路，并且修改设计数据以包括所选择的监视电路。

公开(公告)号：US07489163B2

公开(公告)日：2009-02-10

申请号：US11869921

申请日：2007-10-10

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

公开(公告)号：US07469395B2

公开(公告)日：2008-12-23

申请号：US11952544

申请日：2007-12-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。 第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度 线。

公开(公告)号：US20080285338A1

公开(公告)日：2008-11-20

申请号：US12180776

申请日：2008-07-28

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

公开(公告)号：US20080276034A1

公开(公告)日：2008-11-06

申请号：US12179597

申请日：2008-07-25

申请人： W. Riyon Harding ,  David W. Milton ,  Clarence Rosser Ogilvie ,  Jason E. Rotella ,  Paul M. Schanely ,  Sebastian T. Ventrone

发明人： W. Riyon Harding ,  David W. Milton ,  Clarence Rosser Ogilvie ,  Jason E. Rotella ,  Paul M. Schanely ,  Sebastian T. Ventrone

IPC分类号： G06F13/00

CPC分类号： G06F17/505

摘要： A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

摘要翻译： 可以由无晶圆厂设计公司生成的用于在驻留在集成电路中的核之间传输数据的设计结构。 通过使用位于核心和仲裁器之间的集线器来传输数据。 仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

公开(公告)号：US20080229074A1

公开(公告)日：2008-09-18

申请号：US12127860

申请日：2008-05-28

申请人： Laura F. Miller ,  Pascal A. Nsame ,  Nancy H. Pratt ,  Sebastian T. Ventrone

发明人： Laura F. Miller ,  Pascal A. Nsame ,  Nancy H. Pratt ,  Sebastian T. Ventrone

IPC分类号： G06F9/30

CPC分类号： G06F9/381 ,  G06F9/3867

摘要： A design structure for an integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.

摘要翻译： 一种用于集成电路（IC）的设计结构，包括解码指令，存储指令作为局部回路的阴影锁存器，以及控制解码器和多个阴影锁存器的状态机。 当状态机识别与存储在本地化环路中的指令相同的指令时，其取消对解码器的激活，并激活多个阴影锁存器来取代并执行本地化的循环，代替解码器提供的指令。 另外，提供了一种在IC中提供局部控制高速缓存操作以减少功耗的方法。 该方法包括初始化状态机以控制IC，提供多个阴影锁存器，解码一组指令，检测解码指令的循环，将阴影锁存器中的解码指令的循环缓存为局部循环，检测循环 循环结束信号，并停止局部循环的缓存。

公开(公告)号：US20080151672A1

公开(公告)日：2008-06-26

申请号：US12045744

申请日：2008-03-11

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F12/122

摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

公开(公告)号：US07373567B2

公开(公告)日：2008-05-13

申请号：US10709754

申请日：2004-05-26

申请人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  G01R31/318558 ,  G06F11/261 ,  H03K19/00392

摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic function, such that logic EC is provided within the embedded FPGA structure of the IC chip.

摘要翻译： 一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。 该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。 如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。 识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。 识别故障逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑功能的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。