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    Middle-of-line contacts with varying contact area providing reduced contact resistance
    91.
    发明授权
    Middle-of-line contacts with varying contact area providing reduced contact resistance 有权

    公开(公告)号：US11127825B2

    公开(公告)日：2021-09-21

    申请号：US16361976

    申请日：2019-03-22

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Hari Prasad Amanapu

    IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/78

    摘要： A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.

    INTERCONNECTS WITH SPACER STRUCTURE FOR FORMING AIR-GAPS
    92.
    发明申请
    INTERCONNECTS WITH SPACER STRUCTURE FOR FORMING AIR-GAPS 有权

    公开(公告)号：US20210225691A1

    公开(公告)日：2021-07-22

    申请号：US16744912

    申请日：2020-01-16

    申请人： International Business Machines Corporation

    发明人： Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Chanro Park ,  Chih-Chao Yang

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    摘要： A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.

    Embedded anti-fuses for small scale applications
    95.
    发明授权
    Embedded anti-fuses for small scale applications 有权

    公开(公告)号：US11024577B1

    公开(公告)日：2021-06-01

    申请号：US16746146

    申请日：2020-01-17

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Chih-Chao Yang

    IPC分类号： H01L23/525

    摘要： A method for manufacturing a semiconductor device includes forming first and second interconnect structures on an etch stop layer, wherein the second interconnect structure is spaced apart from the first interconnect structure. The etch stop layer extends between the first and second interconnect structures. In the method, part of the etch stop layer between the first and second interconnect structures is removed. The removing forms a first portion of the etch stop layer extending from under the first interconnect structure toward the second interconnect structure, and a second portion of the etch stop layer extending from under the second interconnect structure toward the first interconnect structure. The first and second portions are spaced apart from each other. A dielectric layer is formed which fills in the spaces between the first and second portions of the etch stop layer and between the first and second interconnect structures.

    BACK END OF LINE STRUCTURES WITH METAL LINES WITH ALTERNATING PATTERNING AND METALLIZATION SCHEMES
    98.
    发明申请
    BACK END OF LINE STRUCTURES WITH METAL LINES WITH ALTERNATING PATTERNING AND METALLIZATION SCHEMES 有权

    公开(公告)号：US20210082714A1

    公开(公告)日：2021-03-18

    申请号：US16570316

    申请日：2019-09-13

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Chanro Park ,  Chih-Chao Yang ,  Kangguo Cheng ,  Juntao Li

    IPC分类号： H01L21/311 ,  H01L23/532 ,  H01L21/768 ,  H01L21/033

    摘要： Techniques are provided to fabricate semiconductor devices. For example, a method includes forming an interconnect structure having a base, a first conductive metal layer disposed on the base; and a first hardmask layer disposed on the first conductive metal layer. Metal lines are formed by subtractive etching. The metal lines have negative tapered sidewalk, and an opening is formed between adjacent metal lines. A first interlevel dielectric layer is deposited in the openings. A portion of the first interlevel dielectric layer is removed to form trench openings having positive tapered sidewalls. A dielectric layer is deposited in one of the openings. A liner layer and a second conducting metal layer are deposited in the other trench openings. The liner layer and the second conductive metal layer are recessed. A second hardmask layer is deposited on a top surface of the liner layer and the second conductive metal layer.

    FLOATING GATE PREVENTION AND CAPACITANCE REDUCTION IN SEMICONDUCTOR DEVICES
    100.
    发明申请
    FLOATING GATE PREVENTION AND CAPACITANCE REDUCTION IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210013322A1

    公开(公告)日：2021-01-14

    申请号：US16504762

    申请日：2019-07-08

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Kangguo Cheng ,  Chanro Park ,  Juntao Li

    IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

    摘要： A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins.