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公开(公告)号：US20200294911A1
公开(公告)日：2020-09-17
申请号：US16352452
申请日：2019-03-13
IPC分类号： H01L23/522 , H01L23/532
摘要： BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure.
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公开(公告)号：US20200219931A1
公开(公告)日：2020-07-09
申请号：US16241866
申请日：2019-01-07
摘要： A substantially flat bottom electrode embedded in a dielectric for magnetoresistive random access memory (MRAM) devices includes pre-filling the contact via prior to filling the trench with tantalum nitride in a via/trench structure. The top surface of the substantially flat bottom electrode is coplanar to the top surface of the dielectric.
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公开(公告)号：US20210035813A1
公开(公告)日：2021-02-04
申请号：US16530165
申请日：2019-08-02
发明人： Hari Prasad Amanapu , Comelius Brown Peethala , Iqbal Rashid Saraf , Raghuveer Reddy Patlolla , Chih-Chao Yang
IPC分类号： H01L21/3105 , H01L21/02 , H01L21/311
摘要： Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.
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公开(公告)号：US10818589B2
公开(公告)日：2020-10-27
申请号：US16352452
申请日：2019-03-13
IPC分类号： H01L23/532 , H01L23/522
摘要： BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure.
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5.发明申请公开(公告)号：US20200303264A1
公开(公告)日：2020-09-24
申请号：US16361976
申请日：2019-03-22
发明人： Chanro Park , Kangguo Cheng , Ruilong Xie , Hari Prasad Amanapu
IPC分类号： H01L21/8238 , H01L21/768 , H01L29/78 , H01L29/66 , H01L29/08 , H01L23/532 , H01L27/092
摘要： A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.
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公开(公告)号：US11127825B2
公开(公告)日：2021-09-21
申请号：US16361976
申请日：2019-03-22
发明人： Chanro Park , Kangguo Cheng , Ruilong Xie , Hari Prasad Amanapu
IPC分类号： H01L29/417 , H01L21/768 , H01L21/8234 , H01L29/78
摘要： A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.
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公开(公告)号：US20210242077A1
公开(公告)日：2021-08-05
申请号：US16776982
申请日：2020-01-30
发明人： Cornelius Brown Peethala , Hari Prasad Amanapu , Raghuveer Reddy Patlolla , Koichi Motoyama , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect. A planarization stop region is formed above the second conductive interconnect and in a third portion of the first dielectric layer.
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公开(公告)号：US11024720B2
公开(公告)日：2021-06-01
申请号：US16351999
申请日：2019-03-13
发明人： Ruilong Xie , Hari Prasad Amanapu , Kangguo Cheng , Chanro Park
IPC分类号： H01L29/45 , H01L29/40 , H01L21/3105 , H01L29/423 , H01L29/417 , H01L29/78
摘要： Techniques regarding non-SAC semiconductor devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a gate positioned adjacent a channel region of a semiconductor body for a field effect transistor. The gate can comprise a metal liner, and wherein the metal liner is an interface between a first metal layer of the gate and a second metal layer of the gate.
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公开(公告)号：US20200343131A1
公开(公告)日：2020-10-29
申请号：US16392996
申请日：2019-04-24
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/3105
摘要： Embodiments of the invention are directed to a method that includes forming a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar. A first interconnect structure having a substantially planar interconnect structure top surface with unintended non-planar regions is formed in the dielectric region. A reinforced planarization process is applied that includes recessing the first interconnect structure top surface to a level that is below the dielectric region top surface and the unintended non-planar region, thereby removing the unintended non-planar region and forming a second interconnect structure having a second interconnect structure top surface that is substantially planar; forming a protective cap on the second interconnect structure top surface, wherein the protective cap has a sustantially planer protective cap top surface; and recessing the dielectric region top surface to a level that is substantially planar with the protective cap top surface.
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公开(公告)号：US20200075746A1
公开(公告)日：2020-03-05
申请号：US16117106
申请日：2018-08-30
IPC分类号： H01L29/66 , H01L29/78 , H01L21/768 , H01L29/08
摘要： A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.
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