公开(公告)号：US09904569B2

公开(公告)日：2018-02-27

申请号：US14986901

申请日：2016-01-04

申请人： International Business Machines Corporation

发明人： Shakti Kapoor

IPC分类号： G06F12/10 ,  G06F12/12 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/123

CPC分类号： G06F12/0862 ,  G06F9/45558 ,  G06F12/1009 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/602 ,  G06F2212/70

摘要： Embodiments herein pre-load memory translations used to perform virtual to physical memory translations in a computing system that switches between virtual machines (VMs). Before a processor switches from executing the current VM to the new VM, a hypervisor may retrieve previously saved memory translations for the new VM and load them into cache or main memory. Thus, when the new VM begins to execute, the corresponding memory translations are in cache rather than in storage. Thus, when these memory translations are needed to perform virtual to physical address translations, the processor does not have to wait to pull the memory translations for slow storage devices (e.g., a hard disk drive).

公开(公告)号：US20170263332A1

公开(公告)日：2017-09-14

申请号：US15063639

申请日：2016-03-08

申请人： International Business Machines Corporation

发明人： Shakti Kapoor

IPC分类号： G11C29/10 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0897 ,  G06F2212/1008 ,  G06F2212/602 ,  G11C29/04 ,  G11C29/10 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/36 ,  G11C2029/0401

摘要： An aspect includes a method of streaming stress testing in a cache memory system. The method includes configuring, by a streaming stress generator, one or more streams of cache lines in the cache memory system to be accessed by a cache prefetch engine of a processor. One or more stream parameters are randomized to vary a streaming stress applied by the one or more streams to the cache memory system. The one or more streams are generated as read or write requests to the cache lines as prefetches from the cache prefetch engine absent a request for the cache lines from a processor core of the processor. A determination is made as to whether any faults are detected while the one or more streams are prefetched.

公开(公告)号：US09720845B2

公开(公告)日：2017-08-01

申请号：US15407135

申请日：2017-01-16

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F12/10 ,  G06F12/1045 ,  G06F12/128 ,  G06F12/0808 ,  G06F12/1009 ,  G06F12/1027

CPC分类号： G06F12/1045 ,  G06F11/263 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/681 ,  G06F2212/683

摘要： A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

公开(公告)号：US20170161208A1

公开(公告)日：2017-06-08

申请号：US15407126

申请日：2017-01-16

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F12/1045 ,  G06F12/0808 ,  G06F12/1009 ,  G06F12/128

CPC分类号： G06F12/1045 ,  G06F11/263 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/681 ,  G06F2212/683

摘要： A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

公开(公告)号：US09594680B1

公开(公告)日：2017-03-14

申请号：US15247381

申请日：2016-08-25

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/12 ,  G06F11/263

CPC分类号： G06F12/1045 ,  G06F11/263 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/681 ,  G06F2212/683

摘要： A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

摘要翻译： 可以在存储在存储器中的表中改变映射。 该表可以将用于一组数据的第一组地址映射到第二组地址。 映射的改变可以包括将第一组地址映射到第三组地址。 响应于映射的改变，可以执行一个或多个刷新操作以使一个或多个地址转换高速缓存内的一个或多个条目无效。 一个或多个条目可以包括第二组地址。 响应于一个或多个刷新操作的执行，可以运行第一测试用例。 第一测试用例可以是测试第一组地址是否映射到第二组地址。

公开(公告)号：US09542290B1

公开(公告)日：2017-01-10

申请号：US15010051

申请日：2016-01-29

申请人： International Business Machines Corporation

发明人： Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F11/263 ,  G11C29/08 ,  G11C29/36 ,  G11C29/10 ,  G06F11/22 ,  G06F3/06

CPC分类号： G06F11/263 ,  G06F3/0617 ,  G06F3/065 ,  G06F3/0683 ,  G06F11/2236 ,  G06F11/2635 ,  G06F12/0806 ,  G06F2212/1024 ,  G06F2212/45 ,  G06F2212/608 ,  G11C29/08 ,  G11C29/10 ,  G11C29/36 ,  G11C29/56004

摘要： Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

摘要翻译： 数据被复制到具有非自然对齐数据边界的存储器高速缓存中，以减少生成用于测试处理器的测试用例所需的时间。 将数据放置在如本文所述的非自然对准的数据边界中允许复制的存储器高速缓存的测试，同时在复制的测试数据的段中保留双字和四字的边界。 这允许为一段内存生成测试用例，然后在整个内存中进行复制，并通过单个测试进行分析，并使用内存缓存中的复制测试数据的下一个链。