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公开(公告)号：US20100226589A1
公开(公告)日：2010-09-09
申请号：US10716386
申请日：2003-11-18
申请人： Nilanjan Mukherjee
发明人： Nilanjan Mukherjee
IPC分类号： G06K9/40
CPC分类号： G06T17/20 , G06T17/205
摘要： A system and method for a hybrid, variational, user-controlled, 3D mesh smoothing for orphaned shell meshes. The smoothing model is based on a variational combination of energy and equi-potential minimization theories. A variety of smoothing techniques for predicting a new location for the node-to-smooth are employed. Each node is moved according to a specific smoothing algorithm so as to keep element included angles, skew and distortion to a minimum. The variational smoother selection logic is based on nodal valency and element connectivity pattern of the node to smooth. Results show its consistency with both quadrilateral and quad-dominant meshes with a significant gain over conventional Laplacian schemes in terms of mesh quality, stability, user control and flexibility.
摘要翻译： 用于孤立壳网格的混合，变体，用户控制的3D网格平滑的系统和方法。 平滑模型基于能量和等效电位最小化理论的变分组合。 采用各种用于预测节点到光滑的新位置的平滑技术。 每个节点根据特定的平滑算法移动，以将元素的夹角，偏斜和失真保持在最小。 变分平滑器选择逻辑基于节点的节点价值和元素连通性模式来平滑。 在网格质量，稳定性，用户控制和灵活性方面，结果表明其与四边形和四重主要网格的一致性在传统拉普拉斯算法方面具有显着的增益。
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92.发明授权Scheduling the concurrent testing of multiple cores embedded in an integrated circuit 有权调度嵌入在集成电路中的多个内核的并发测试公开(公告)号：US06934897B2
公开(公告)日：2005-08-23
申请号：US10210794
申请日：2002-07-31
申请人： Nilanjan Mukherjee , Chien-Chung Tsai , Wu-Tung Cheng , Omer Ghazi Samman , Yahya M. Z. Mustafa , Paul J. Reuter , Yu Huang , Sudhakar Mannapuram Reddy
发明人： Nilanjan Mukherjee , Chien-Chung Tsai , Wu-Tung Cheng , Omer Ghazi Samman , Yahya M. Z. Mustafa , Paul J. Reuter , Yu Huang , Sudhakar Mannapuram Reddy
IPC分类号： G01R31/3193 , G01R31/28
CPC分类号： G01R31/3193
摘要： Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.
摘要翻译： 描述了用于调度嵌入在集成电路中的多个核的并发测试的方法。 通过将问题解决为二进制包装问题并使用修改后的二维或三维二进制包装启发式来进行测试调度。 多个核心的测试表示为至少用于测试核心和核心测试时间的集成电路引脚的功能。 表示可以包括测试核心所需的峰值功率的第三维度。 测试计划表示为具有至少集成电路引脚和集成电路测试时间的尺寸的存储区。 箱可以包括峰值功率的第三维度。 多核的调度是通过将多个核心测试表示拟合到bin来实现的。
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公开(公告)号：US08861401B2
公开(公告)日：2014-10-14
申请号：US13438794
申请日：2012-04-03
IPC分类号： H04Q11/00
CPC分类号： H04L45/745 , H04L49/3009 , H04L61/2038 , H04L61/6022
摘要： In one embodiment, a system includes at least one processor which includes logic configured for receiving a request to assign a media access control (MAC) address to a device on a port, logic configured for determining the MAC address to assign to the device based at least partially on the port, and logic configured for sending a response to the request with the MAC address. In another embodiment, a computer program product for assigning a MAC address includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code including computer readable program code configured for determining, without using a look-up table, a MAC address to assign to a device and computer readable program code configured for sending the MAC address to the device. Other systems, methods, and computer program products are presented according to more embodiments.
摘要翻译： 在一个实施例中，系统包括至少一个处理器，其包括被配置为接收向端口上的设备分配媒体访问控制（MAC）地址的请求的逻辑，被配置为基于 最少部分地在端口上，以及被配置为用于发送具有MAC地址的请求的响应的逻辑。 在另一个实施例中，一种用于分配MAC地址的计算机程序产品包括具有其中包含的计算机可读程序代码的计算机可读存储介质，该计算机可读程序代码包括计算机可读程序代码，其被配置用于在不使用查找表的情况下确定 分配给设备的MAC地址和配置为将MAC地址发送到设备的计算机可读程序代码。 根据更多实施例呈现其他系统，方法和计算机程序产品。
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94.发明授权Techniques for executing normally interruptible threads in a non-preemptive manner 有权以非抢先方式执行正常可中断线程的技术公开(公告)号：US08856801B2
公开(公告)日：2014-10-07
申请号：US13602365
申请日：2012-09-04
CPC分类号： G06F9/52 , G06F9/4881 , G06F2209/486
摘要： A technique for executing normally interruptible threads of a process in a non-preemptive manner includes in response to a first entry associated with a first message for a first thread reaching a head of a run queue, receiving, by the first thread, a first wake-up signal. In response to receiving the wake-up signal, the first thread waits for a global lock. In response to the first thread receiving the global lock, the first thread retrieves the first message from an associated message queue and processes the retrieved first message. In response to completing the processing of the first message, the first thread transmits a second wake-up signal to a second thread whose associated entry is next in the run queue. Finally, following the transmitting of the second wake-up signal the first thread releases the global lock.
摘要翻译： 用于以非预先方式执行进程的正常可中断线程的技术包括响应于与第一消息相关联的第一条目，用于第一线程到达运行队列的头部，由第一线程接收第一唤醒 -up信号。 响应于接收到唤醒信号，第一个线程等待一个全局锁定。 响应于接收全局锁的第一线程，第一线程从相关联的消息队列中检索第一消息并处理检索到的第一消息。 响应于完成第一消息的处理，第一线程向第二线程发送第二唤醒信号，该第二线程的相关条目在下一个运行队列中。 最后，在发送第二个唤醒信号之后，第一个线程释放全局锁。
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95.发明授权公开(公告)号：US08792489B2
公开(公告)日：2014-07-29
申请号：US13434705
申请日：2012-03-29
申请人： Sushma Anantharam , Stephan Benny , Nirapada Ghosh , Dayavanti G. Kamath , Keshav G. Kamble , Dar-Ren Leu , Chandarani J. Mendon , Nilanjan Mukherjee , Vijoy Pandey , Nandakumar Peethambaram
发明人： Sushma Anantharam , Stephan Benny , Nirapada Ghosh , Dayavanti G. Kamath , Keshav G. Kamble , Dar-Ren Leu , Chandarani J. Mendon , Nilanjan Mukherjee , Vijoy Pandey , Nandakumar Peethambaram
摘要： A communication protocol in a layer two (L2) network switch comprises, in response to a service request by a source node, registering the source node for packet communication service. The protocol further comprises forwarding one or more packets from the registered source node to one or more destination nodes. The protocol further comprises receiving packets from one or more destination nodes and forwarding each received packet to a corresponding registered node.
摘要翻译： 第二层（L2）网络交换机中的通信协议响应于源节点的服务请求，注册用于分组通信服务的源节点。 协议还包括将一个或多个分组从注册的源节点转发到一个或多个目的地节点。 该协议还包括从一个或多个目的地节点接收分组，并将每个接收到的分组转发到相应的注册节点。
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公开(公告)号：US20130258899A1
公开(公告)日：2013-10-03
申请号：US13438794
申请日：2012-04-03
IPC分类号： H04L12/28
CPC分类号： H04L45/745 , H04L49/3009 , H04L61/2038 , H04L61/6022
摘要： In one embodiment, a system includes at least one processor which includes logic configured for receiving a request to assign a media access control (MAC) address to a device on a port, logic configured for determining the MAC address to assign to the device based at least partially on the port, and logic configured for sending a response to the request with the MAC address. In another embodiment, a computer program product for assigning a MAC address includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code including computer readable program code configured for determining, without using a look-up table, a MAC address to assign to a device and computer readable program code configured for sending the MAC address to the device. Other systems, methods, and computer program products are presented according to more embodiments.
摘要翻译： 在一个实施例中，系统包括至少一个处理器，其包括被配置为接收向端口上的设备分配媒体访问控制（MAC）地址的请求的逻辑，被配置为基于 最少部分地在端口上，以及被配置为用于发送具有MAC地址的请求的响应的逻辑。 在另一个实施例中，一种用于分配MAC地址的计算机程序产品包括具有其中包含的计算机可读程序代码的计算机可读存储介质，该计算机可读程序代码包括计算机可读程序代码，其被配置用于在不使用查找表的情况下确定 分配给设备的MAC地址和配置为将MAC地址发送到设备的计算机可读程序代码。 根据更多实施例呈现其他系统，方法和计算机程序产品。
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公开(公告)号：US20120320926A1
公开(公告)日：2012-12-20
申请号：US13314455
申请日：2011-12-08
IPC分类号： H04L12/56
CPC分类号： H04L41/0654 , H04L45/245 , H04L45/28 , H04L45/66 , Y02D50/30
摘要： Each of first and second bridges of a data network having respective links to an external node implement a network bridge component that forwards traffic inside the data network and a virtual bridge component that forwards traffic outside of the data network. A virtual bridge is formed including the virtual bridge components of the first and second bridges and an interswitch link (ISL) between the virtual bridge components of the first and second bridges. Data frames are communicated with each of multiple external network nodes outside the data network via a respective one of multiple link aggregation groups all commonly supported by the virtual bridge.
摘要翻译： 具有到外部节点的各个链接的数据网络的每个第一和第二桥接器实现转发数据网络内的业务的网桥组件，以及在数据网络之外转发业务的虚拟桥组件。 形成虚拟桥，包括第一和第二桥的虚拟桥组件和第一和第二桥的虚拟桥组件之间的交叉连接（ISL）。 数据帧通过虚拟桥通常支持的多个链路聚合组中的相应一个，与数据网络外部的多个外部网络节点中的每一个进行通信。
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公开(公告)号：US20120320800A1
公开(公告)日：2012-12-20
申请号：US13315463
申请日：2011-12-09
IPC分类号： H04L12/28
CPC分类号： H04L41/0654 , H04L45/245 , H04L45/28 , H04L45/66 , Y02D50/30
摘要： A switch of a data network implements both a bridge and a virtual bridge. In response to receipt of a data frame by the switch from an external link, the switch performs a lookup in a data structure using a source media access control (SMAC) address specified by the data frame. The switch determines if the external link is configured in a link aggregation group (LAG) and if the SMAC address is newly learned. In response to a determination that the external link is configured in a LAG and the SMAC address is newly learned, the switch associates the SMAC with the virtual bridge and communicates the association to a plurality of bridges in the data network.
摘要翻译： 数据网络的交换机既实现了桥接器又实现了一个虚拟桥接器。 响应于交换机从外部链路接收到数据帧，交换机使用由数据帧指定的源媒体访问控制（SMAC）地址在数据结构中执行查找。 交换机确定在链路聚合组（LAG）中是否配置了外部链路，如果新学习到SMAC地址。 响应于外部链路被配置在LAG中并且新学习到SMAC地址的确定，交换机将SMAC与虚拟网桥相关联，并将该关联传送到数据网络中的多个网桥。
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公开(公告)号：US20120093035A1
公开(公告)日：2012-04-19
申请号：US13276966
申请日：2011-10-19
IPC分类号： H04L12/28
CPC分类号： H04L49/351 , H04L49/3054 , H04L49/70
摘要： A method and system for configuring communications over a physical communication link connected between a physical port of a network switch and a physical port of a physical network interface on an end station. The communication link between the physical port of the network switch and the physical port of the physical network interface is logically partitioned into a number of channels of communication. For each channel, a channel profile is generated that defines properties of that channel. The physical network interface is instructed to self-configure such that the physical network interface is able to communicate with the network switch over each channel in accordance with the channel profile defined for that channel.
摘要翻译： 一种用于通过连接在网络交换机的物理端口与终端站的物理网络接口的物理端口之间的物理通信链路来配置通信的方法和系统。 网络交换机的物理端口与物理网络接口的物理端口之间的通信链路在逻辑上划分为多个通信通道。 对于每个通道，生成定义该通道的属性的通道配置文件。 指示物理网络接口自配置，使得物理网络接口能够根据为该信道定义的信道简档，通过每个信道与网络交换机进行通信。
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100.发明授权公开(公告)号：US07428680B2
公开(公告)日：2008-09-23
申请号：US11283527
申请日：2005-11-18
申请人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译： 公开了可编程存储器内置的自检（MBIST）方法，装置和系统。 所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。
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