公开(公告)号：US20120326168A1

公开(公告)日：2012-12-27

申请号：US13608250

申请日：2012-09-10

申请人： Thomas N. Adam ,  Judson R. Holt ,  Alexander Reznicek ,  Thomas A. Wallner

发明人： Thomas N. Adam ,  Judson R. Holt ,  Alexander Reznicek ,  Thomas A. Wallner

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78687

摘要： A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.

摘要翻译： 一种形成半导体器件的方法，包括在含锗硅层上提供包括半导体层的衬底，并在半导体层的沟道部分的表面上形成栅极结构。 阱沟槽被蚀刻到栅极结构的相对侧上的半导体层中。 用于形成阱沟槽的蚀刻工艺形成在栅极结构下延伸的底切区域，并且对含锗硅层具有选择性。 应力诱导半导体材料被外延生长以填充阱沟槽的至少一部分以提供应力诱导源区域和具有平面基极的应力诱导漏极区域中的至少一个。

公开(公告)号：US20120319166A1

公开(公告)日：2012-12-20

申请号：US13161913

申请日：2011-06-16

申请人： Thomas N. Adam ,  Judson R. Holt ,  Alexander Reznicek ,  Thomas A. Wallner

发明人： Thomas N. Adam ,  Judson R. Holt ,  Alexander Reznicek ,  Thomas A. Wallner

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78687

摘要： A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.

公开(公告)号：US20120205716A1

公开(公告)日：2012-08-16

申请号：US13028316

申请日：2011-02-16

申请人： Thomas N. Adam ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Douglas C. LaTulipe, JR. ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Douglas C. LaTulipe, JR. ,  Alexander Reznicek

IPC分类号： H01L29/165 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： Epitaxially grown extension regions are disclosed for scaled CMOS devices. Semiconductor devices are provided that comprise a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises at least a channel layer formed below the gate stack. One or more etched extension regions containing an epitaxially grown dopant are provided in the channel layer.

摘要翻译： 公开了用于缩放CMOS器件的外延生长扩展区。 提供了包括在硅衬底上具有栅极堆叠的场效应晶体管（FET）结构的半导体器件，其中场效应晶体管结构至少包括形成在栅极堆叠下方的沟道层。 在沟道层中设置一个或多个含有外延生长掺杂剂的蚀刻延伸区。

公开(公告)号：US20120003819A1

公开(公告)日：2012-01-05

申请号：US13135031

申请日：2011-06-23

申请人： Terry Arthur Francis ,  Satoshi Hasaka ,  Paul David Brabant ,  Robert Torres, JR. ,  He Hong ,  Alexander Reznicek ,  Thomas N. Adam ,  Devendra K. Sadana

发明人： Terry Arthur Francis ,  Satoshi Hasaka ,  Paul David Brabant ,  Robert Torres, JR. ,  He Hong ,  Alexander Reznicek ,  Thomas N. Adam ,  Devendra K. Sadana

IPC分类号： H01L21/205

CPC分类号： H01L21/02532 ,  C23C16/30 ,  C23C16/325 ,  C30B25/02 ,  C30B29/06 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.

摘要翻译： 本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速 小于约550℃，压力范围为约10mTorr-200Torr。 此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳 。

公开(公告)号：US20110263104A1

公开(公告)日：2011-10-27

申请号：US12766859

申请日：2010-04-24

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.

摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。 选择身体为Si，Ge或其合金混合物。 选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。 这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。 该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。 在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

公开(公告)号：US07655551B2

公开(公告)日：2010-02-02

申请号：US12127171

申请日：2008-05-27

申请人： Yaocheng Liu ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Yaocheng Liu ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/28035 ,  H01L21/32155 ,  H01L29/4916

摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

摘要翻译： 提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。 本发明还提供了包括例如nFET和/或pFET的CMOS结构，其利用本文所述的气相掺杂技术制造。

公开(公告)号：US07498235B2

公开(公告)日：2009-03-03

申请号：US11924207

申请日：2007-10-25

申请人： Tze-chiang Chen ,  Guy M. Cohen ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Tze-chiang Chen ,  Guy M. Cohen ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

摘要翻译： 提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。 在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

公开(公告)号：US07473626B2

公开(公告)日：2009-01-06

申请号：US11402177

申请日：2006-04-11

申请人： Yaocheng Liu ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Yaocheng Liu ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/28035 ,  H01L21/32155 ,  H01L29/4916

摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

摘要翻译： 提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。 本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

公开(公告)号：US20080254594A1

公开(公告)日：2008-10-16

申请号：US12143912

申请日：2008-06-23

申请人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

发明人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

IPC分类号： H01L21/30

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20080206958A1

公开(公告)日：2008-08-28

申请号：US12115731

申请日：2008-05-06

申请人： Victor Chan ,  Massimo V. Fischetti ,  John M. Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul M. Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo V. Fischetti ,  John M. Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul M. Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/20

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

摘要翻译： 本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。 本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。 本发明的另一方面涉及形成本发明的半导体材料的方法。 本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。