摘要:
Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
摘要:
A swing limiter comprises a logic circuit including a first pull-up transistor and a first pull-down transistor connected between first and second nodes and which generate an output signal; a second pull-up transistor connected between a first power voltage and the first node; a second pull-down transistor connected between the second node and a second power voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage; and a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage.
摘要:
A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.
摘要:
A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.
摘要:
A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.
摘要:
A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.
摘要:
A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.
摘要:
An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.
摘要:
A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.
摘要:
A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.