公开(公告)号：US07496724B2

公开(公告)日：2009-02-24

申请号：US11453674

申请日：2006-06-14

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： G06F13/14

CPC分类号： G06F11/2069 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0689 ,  G06F2206/1012

摘要： Optimal performance tuning is enabled by avoiding the deterioration in the performance of a storage system caused by an erroneous setting in a tuning parameter. The storage system has a primary volume provided as an operational volume to a host computer, and a secondary volume capable of forming a copy-pair with the primary volume. When the load demanded in executing I/O processing to the secondary volume set with a second tuning parameter is lighter than the load demanded in executing I/O processing to the primary volume set with a first tuning parameter, the storage controller switches the primary/secondary relationship between the primary volume and secondary volume and provides the secondary volume as the operational volume to the host computer.

摘要翻译： 通过避免由调谐参数中的错误设置引起的存储系统的性能的劣化，能够实现最佳性能调谐。 存储系统具有作为主计算机的操作卷提供的主卷，以及能够与主卷形成副本对的辅助卷。 当对具有第二调谐参数设置的辅助卷执行I / O处理所需的负载比在执行具有第一调谐参数的主卷集的I / O处理所需的负载更轻时，存储控制器将主/ 主卷和次卷之间的辅助关系，并将次要卷提供给主计算机的操作卷。

公开(公告)号：US20080059750A1

公开(公告)日：2008-03-06

申请号：US11581569

申请日：2006-10-17

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： G06F12/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0683 ,  G06F11/3409 ,  G06F11/3461

摘要： A computer system includes a host computer; a first storage system that processes an I/O request issued by the host computer; and a second storage system that receives host I/O information and performance information from the first storage system and reproduces, based on the host I/O information and performance information, the internal processing conditions of the first storage system at the time the I/O request was processed, thereby simulating the I/O performance of the first storage system.

摘要翻译： 计算机系统包括主计算机; 处理由主机发出的I / O请求的第一存储系统; 以及第二存储系统，其从所述第一存储系统接收主机I / O信息和性能信息，并且基于所述主机I / O信息和性能信息，再现所述第一存储系统的内部处理条件， O请求进行处理，从而模拟第一个存储系统的I / O性能。

公开(公告)号：US20070208910A1

公开(公告)日：2007-09-06

申请号：US11404633

申请日：2006-04-14

申请人： Hideyuki Koseki ,  Junji Ogawa ,  Yutaka Nakagawa

发明人： Hideyuki Koseki ,  Junji Ogawa ,  Yutaka Nakagawa

IPC分类号： G06F12/16

CPC分类号： G06F3/0638 ,  G06F3/061 ,  G06F3/0683

摘要： A storage device according to the present invention has a first volume for storing discontinuous data transmitted from a host computer and a second volume for storing continuous data produced by address-converting discontinuous data, and includes: a data storing unit for converting the discontinuous data transmitted from the host computer into the continuous data and storing the continuous data in one of a plurality of third volumes formed by dividing up the second volume; a data management unit for managing transfer target data that has to be transferred from the third to the first volume, from among the discontinuous data stored in the third volume by the data storing unit; and a volume clearance unit for clearing the third volume having the smallest amount of transfer target data managed by the data management unit by transferring the transfer target data in the relevant third volume to the first volume.

摘要翻译： 根据本发明的存储装置具有用于存储从主计算机发送的不连续数据的第一卷和用于存储通过地址转换不连续数据产生的连续数据的第二卷，包括：数据存储单元，用于将发送的不连续数据 从所述主计算机进入连续数据，并将所述连续数据存储在通过划分所述第二卷而形成的多个第三卷之一中; 数据管理单元，用于从数据存储单元从第三卷中存储的不连续数据中管理必须从第三卷到第一卷的传送目标数据; 以及体积清除单元，用于通过将有关的第三卷中的传送目标数据传送到第一卷来清除由数据管理单元管理的具有最小量的传送目标数据的第三卷。

公开(公告)号：US06493394B2

公开(公告)日：2002-12-10

申请号：US10076526

申请日：2002-02-19

申请人： Hirotaka Tamura ,  Miyoshi Saito ,  Kohtaroh Gotoh ,  Shigetoshi Wakayama ,  Junji Ogawa ,  Hisakatsu Araki ,  Tsz-shing Cheung

发明人： Hirotaka Tamura ,  Miyoshi Saito ,  Kohtaroh Gotoh ,  Shigetoshi Wakayama ,  Junji Ogawa ,  Hisakatsu Araki ,  Tsz-shing Cheung

IPC分类号： H04B300

CPC分类号： H04L25/0276 ,  G06F13/4243 ,  H04L25/0278 ,  H04L25/0282 ,  H04L25/0288 ,  H04L25/497 ,  Y02D10/14 ,  Y02D10/151

摘要： A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

公开(公告)号：US06333883B2

公开(公告)日：2001-12-25

申请号：US09768465

申请日：2001-01-25

申请人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

发明人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C11/4091

摘要： A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

摘要翻译： 为每个存储器块191和192提供的恢复电路24具有寄存器和用于选择当前行地址和寄存器的输出之一的选择器，将选择器的输出提供给字解码器26.现在 行地址保存在其中一个寄存器中。 当由读出放大器15开始放大时，连接在位线BL1和* BL1与读出放大器15之间的传输门10和11被截止以减小读出放大器15的负载，放大的信号被存储在缓冲器 存储单元电路18，并且通过省略对存储单元12的恢复来完成访问。虽然没有选择存储单元块191，但是保持在缓冲存储单元电路18中的数据被存储到由 所选寄存器。 读出放大器15具有PMOS和NMOS读出放大器。 具有一对交叉耦合PMOS晶体管和一对传输栅极的PMOS读出放大器，PMOS晶体管的源极的电位固定在Vii处，当传输门断开时，其工作在直接感测模式，而 然后通过打开传输门来作为通常的PMOS读出放大器。 类似于NMOS读出放大器。

公开(公告)号：US5973750A

公开(公告)日：1999-10-26

申请号：US175027

申请日：1998-10-20

申请人： Junji Ogawa ,  Tadayuki Aoyama ,  Takahide Yoshioka

发明人： Junji Ogawa ,  Tadayuki Aoyama ,  Takahide Yoshioka

IPC分类号： H04N17/00 ,  H04H1/00 ,  H04H60/31 ,  H04H60/43 ,  H04H60/59 ,  H04N7/20 ,  H04N5/50

CPC分类号： H04H60/43 ,  H04H60/31 ,  H04H60/59

摘要： A television channel selection monitoring apparatus for identifying the broadcast channel to which a television receiver means is tuned at any given time is disclosed. Instead of relying for the channel identification on the local oscillation frequency at the tuner of such television receiver means, the apparatus of the present invention utilizes the recognition of the channel identification number superimposed on the video signal received through the selected channel so that the image of the superimposed channel number may appear, for a certain duration following the channel selection, at a predetermined area of the image corresponding to the video signal.

摘要翻译： 公开了一种电视频道选择监视装置，用于识别在任何给定时间调谐电视接收机装置的广播频道。 本发明的装置不是依赖于在这种电视接收机装置的调谐器处的本地振荡频率上的信道识别，而是利用叠加在通过所选择的信道接收的视频信号上的信道标识号的识别，使得 在频道选择之后的某个持续时间内可以在对应于视频信号的图像的预定区域处出现叠加的频道号码。

公开(公告)号：US5909142A

公开(公告)日：1999-06-01

申请号：US906143

申请日：1997-08-05

申请人： Kenichi Kawasaki ,  Junji Ogawa

发明人： Kenichi Kawasaki ,  Junji Ogawa

IPC分类号： G01R31/26 ,  G01R31/28 ,  G05F1/46 ,  H01L21/66 ,  G05F1/10

CPC分类号： G05F1/465

摘要： A semiconductor integrated circuit device includes a flat-range voltage supply unit which steps down an external power supply voltage and generates a resultant, flat-range voltage, and a burn-in voltage supply unit which generates a burn-in voltage depending on the external power supply voltage. A switching unit selects either the flat-range voltage or the burn-in voltage, a selected voltage being supplied to an internal circuit. A switching instruction unit includes switches and generates a switching instruction signal by an ON/OFF control of the switches. A switching control unit controls the switching unit in accordance with the switching instruction signal.

摘要翻译： 一种半导体集成电路器件，包括：平坦电压供给单元，其降低外部电源电压并产生合成的平均电压;以及老化电压供给单元，其根据外部电压产生老化电压 电源电压。 开关单元选择平均电压或老化电压，所选择的电压被提供给内部电路。 开关指令单元包括开关，并通过开关的ON / OFF控制产生开关指令信号。 切换控制单元根据切换指示信号来控制切换单元。

公开(公告)号：US5163102A

公开(公告)日：1992-11-10

申请号：US671079

申请日：1991-03-18

申请人： Masao Yamazaki ,  Fumitoshi Yoshimura ,  Kenzo Nozaki ,  Junji Ogawa ,  Junichi Naemura

发明人： Masao Yamazaki ,  Fumitoshi Yoshimura ,  Kenzo Nozaki ,  Junji Ogawa ,  Junichi Naemura

IPC分类号： G06T1/00 ,  G01N21/88

CPC分类号： G01N21/8806

摘要： An image recognition apparatus includes a light source including a plurality of light emitting diodes having different wavelengths, for illuminating an object, a driver for selectively operating the light emitting diodes and adjusting the brightness thereof, an image pick-up device for photoelectrically transferring the light reflected from the object into an image signal, and an image decision device for comparing a reference image signal with the image signal obtained by the image pick-up device and then deciding whether an image corresponding to the obtained image signal is clearer than an image corresponding to the reference image signal, the image decision device making the driver sequentially operates the light emitting diodes and change the brightness thereof in such a manner that the image corresponding to the image signal is clearer than the image corresponding to the reference image signal.

摘要翻译： 一种图像识别装置，包括：包括多个具有不同波长的发光二极管的光源，用于照射物体;驱动器，用于选择性地操作发光二极管并调节其亮度;图像拾取装置，用于光电转换光 从物体反射成图像信号，以及图像判定装置，用于将参考图像信号与由图像拾取装置获得的图像信号进行比较，然后判定与获得的图像信号相对应的图像是否比对应的图像更清晰 使参考图像信号，使得驱动器的图像判定装置顺序地操作发光二极管并且以使得对应于图像信号的图像比对应于参考图像信号的图像更清晰的方式改变其亮度。

公开(公告)号：US4896301A

公开(公告)日：1990-01-23

申请号：US143477

申请日：1988-01-13

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06T1/60 ,  G11C8/00 ,  G11C11/401

CPC分类号： G11C8/00 ,  G06F12/0207

摘要： An improved semiconductor memory device provided with an address scramble unit in addition to a multidirection data selection unit. The address scramble unit converts an external address having an addressing linearity regardless of a complex multidirection data selection into an internal address used by the multidirection data selection unit. A plurality of memory cells are connected between a plurality of word lines and a plurality of bit lines to form a logical space; a plurality of boundaries being defined in a direction thereof. Each boundary includes a plurality of segments each defining a plurality of simultaneously accessible bit data. The multidirection data selection unit outputs a data in response to a segment designation address a direction signal and a segment internal address, from a boundary data selected by a row address.

公开(公告)号：US4720815A

公开(公告)日：1988-01-19

申请号：US864248

申请日：1986-05-19

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： G11C19/28 ,  G11C19/18 ,  G11C13/00

CPC分类号： G11C19/184

摘要： A semiconductor memory device in the form of a shift register is supplied with two-phase clock signals. One of the two-phase clock signal lines is connected to even order shift register elements of the shift register, and the other of the two-phase clock signal lines is connected to odd order shift register elements of the shift register. Each of the shift register elements includes an output node, a gate connected between the output node and a clock signal supplying node, a charge-up circuit responsive to the output signal of the preceding shift register element for preliminarily charging a control node of the gate, and a discharge circuit responsive to the output of the succeeding shift register element for releasing the charge of the control node of the gate.

摘要翻译： 以移位寄存器形式的半导体存储器件被提供有两相时钟信号。 两相时钟信号线之一连接到移位寄存器的偶数位移寄存器元件，而另一个两相时钟信号线连接到移位寄存器的奇数位移寄存器元件。 每个移位寄存器元件包括输出节点，连接在输出节点和时钟信号提供节点之间的门，响应于前一移位寄存器元件的输出信号的充电电路，用于预先对门的控制节点充电 以及放电电路，其响应于后续移位寄存器元件的输出，用于释放栅极的控制节点的电荷。