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    Signal transmission system having a timing adjustment circuit
    5.
    发明授权
    Signal transmission system having a timing adjustment circuit 有权
    信号传输系统具有定时调整电路

    公开(公告)号：US06484268B2

    公开(公告)日：2002-11-19

    申请号：US09794084

    申请日：2001-02-28

    申请人： Hirotaka Tamura ,  Hisakatsu Araki ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    发明人： Hirotaka Tamura ,  Hisakatsu Araki ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    IPC分类号： G06F104

    CPC分类号： H04L7/0337 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03K2005/00052 ,  H04L7/0025

    摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

    摘要翻译： 半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。 定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号 的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。 以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

    Phase interpolator for a timing signal generating circuit
    8.
    发明授权
    Phase interpolator for a timing signal generating circuit 有权
    用于定时信号发生电路的相位内插器

    公开(公告)号：US08065553B2

    公开(公告)日：2011-11-22

    申请号：US12358861

    申请日：2009-01-23

    申请人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    发明人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F1/24 ,  H03J7/04

    CPC分类号： H04L7/0337 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03K2005/00052 ,  H04L7/0025

    摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

    摘要翻译： 半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。 定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号 的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。 以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

    Timing signal generating circuit with a master circuit and slave circuits
    9.
    发明授权
    Timing signal generating circuit with a master circuit and slave circuits 有权
    具有主电路和从电路的定时信号发生电路

    公开(公告)号：US07496781B2

    公开(公告)日：2009-02-24

    申请号：US10278800

    申请日：2002-10-24

    申请人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    发明人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    IPC分类号： G06F1/04 ,  G05F1/12 ,  H03L7/06

    CPC分类号： H04L7/0337 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03K2005/00052 ,  H04L7/0025

    摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

    摘要翻译： 半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。 定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号 的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。 以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

    Destructive read type memory circuit, restoring circuit for the same and sense amplifier
    10.
    发明授权
    Destructive read type memory circuit, restoring circuit for the same and sense amplifier 有权

    公开(公告)号：US06205076B1

    公开(公告)日：2001-03-20

    申请号：US09276690

    申请日：1999-03-26

    申请人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

    发明人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

    IPC分类号： G11C700

    CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C11/4091

    摘要： A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.