公开(公告)号：US07911823B2

公开(公告)日：2011-03-22

申请号：US12123827

申请日：2008-05-20

申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/12 ,  G11C8/08

CPC分类号： G11C11/36

摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

公开(公告)号：US20110032746A1

公开(公告)日：2011-02-10

申请号：US12849407

申请日：2010-08-03

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一线; 与第一线相交的多个第二线; 以及多个存储单元，每个存储单元包括设置在第一和第二行的交叉点处的可变电阻元件，并且被配置为以非易失性方式存储作为数据的电可重写电阻值;以及控制单元，被配置为检测电流量 当访问存储器单元时流过第一行，并且基于电流量来调整第一行或第二行的电压。

公开(公告)号：US20110018879A1

公开(公告)日：2011-01-27

申请号：US12923512

申请日：2010-09-24

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G06T11/20

CPC分类号： G03F1/36

摘要： In a first process of a pattern generation method, a first segment to be handled which is not on a grid is extracted. In a second process, a second segment opposite to the first segment is extracted. In a third process, whether the second segment is on the grid is determined. In FIG. 1A, the second segment is not on the grid. Therefore, in a fourth process the first segment is shifted onto the grid under a determined condition. In addition, the second segment is shifted onto the grid so that line width between the first segment and the second segment is closest to target line width.

摘要翻译： 在图案生成方法的第一处理中，提取不在网格上的要处理的第一片段。 在第二过程中，提取与第一段相对的第二段。 在第三过程中，确定第二段是否在网格上。 在图 如图1A所示，第二段不在网格上。 因此，在第四过程中，第一段在确定的条件下移动到网格上。 此外，第二段被转移到网格上，使得第一段和第二段之间的线宽最接近目标线宽。

公开(公告)号：US07817457B2

公开(公告)日：2010-10-19

申请号：US12132972

申请日：2008-06-04

申请人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohshima

发明人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohshima

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/72

摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

摘要翻译： 根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

公开(公告)号：US07733702B2

公开(公告)日：2010-06-08

申请号：US11954813

申请日：2007-12-12

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344

摘要： A semiconductor memory device includes a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line and a source line, respectively. The semiconductor memory device also includes dummy cells inserted in the NAND cell unit adjacent to the first and second selection transistors, respectively. The dummy cells in the NAND cell unit are erased simultaneously with the memory cells under a weaker erase potential condition than that for the memory cells and set in a higher threshold distribution than an erased state of the memory cells.

摘要翻译： 半导体存储器件包括NAND单元单元的存储单元阵列。 NAND单元单元包括串联连接的多个电可擦除可编程非易失性存储单元，以及分别将存储单元的两端连接到位线和源极线的第一和第二选择晶体管。 半导体存储器件还包括分别插入与NAND单元单元相邻的第一和第二选择晶体管的虚拟单元。 与存储单元相比，NAND单元单元中的虚设单元与存储单元同时擦除，而且存储单元的擦除电位低于存储单元，并且设置在比存储单元的擦除状态更高的阈值分布。

公开(公告)号：US20090290414A1

公开(公告)日：2009-11-26

申请号：US12512829

申请日：2009-07-30

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5642

摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.

摘要翻译： 非易失性半导体存储器件包括具有串联连接的多个多电平存储单元的存储单元阵列。 多个多级存储器单元形成多个阈值分布，每个阈值分布对应于较低位的状态和高位的状态，其中低位和高位分别构成下部页面和上部页面 。 较低位的状态将阈值分布分为两组，高位的状态进一步将两组中的每一组进行二分。 当对上部页面的存储单元进行编程时，当对下部页面的存储单元进行编程时，较高电位被施加到与所选字线相邻的未选择字线，而不是应用于未选择的字线。

公开(公告)号：US20090061607A1

公开(公告)日：2009-03-05

申请号：US12202708

申请日：2008-09-02

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： H01L21/28 ,  G03F1/00

CPC分类号： G03F1/32 ,  H01L21/28035

摘要： According to an aspect of an embodiment, a method of manufacturing a photomask has forming a laminate over a transparent substrate, the laminate having a light-shielding layer and a hard mask layer, forming a negative resist layer over the laminate, exposing and developing the negative resist layer over the laminate to form a first resist pattern having a main pattern in a main exposure area surrounded by an outer area, etching the hard mask layer using the first resist pattern as an etching mask to form a hard mask pattern, removing the first resist pattern from the laminate; forming a positive resist layer covering the hard mask pattern over the transparent substrate, exposing and developing the positive resist layer to form a second resist pattern, the second resist pattern and a light-shielding pattern disposed in the outer area and forming an opening disclosing the hard mask pattern.

摘要翻译： 根据实施方式的一个方面，制造光掩模的方法在透明基板上形成层压体，该层压体具有遮光层和硬掩模层，在层叠体上形成负的抗蚀剂层，曝光和显影 负层抗蚀剂层，以形成在由外部区域围绕的主曝光区域中具有主图案的第一抗蚀剂图案，使用第一抗蚀剂图案蚀刻硬掩模层作为蚀刻掩模以形成硬掩模图案，去除 来自层压板的第一抗蚀剂图案; 在所述透明基板上形成覆盖所述硬掩模图案的正性抗蚀剂层，暴露并显影所述正性抗蚀剂层以形成第二抗蚀剂图案，所述第二抗蚀剂图案和设置在所述外部区域中的遮光图案形成开口， 硬掩模图案。

公开(公告)号：US20090052227A1

公开(公告)日：2009-02-26

申请号：US12118064

申请日：2008-05-09

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/06

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

公开(公告)号：US07420843B2

公开(公告)日：2008-09-02

申请号：US11512325

申请日：2006-08-30

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/32 ,  G11C2211/565

摘要： A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, a source line coupled to one end of the NAND cell unit, and a bit line coupled to the other end of the NAND cell unit, wherein the NAND cell unit is biased in a data write mode as follows: a write voltage Vpgm is applied to a control gate of a selected memory cell in the NAND cell unit; a channel-isolating voltage is applied to control gates of non-selected memory cells disposed on the source line side of the selected memory cell at intervals of a certain number of memory cells; and a write medium voltage Vm lower than Vpgm is applied to control gates of the remaining non-selected memory cells.

摘要翻译： 一种非易失性半导体存储器件，包括具有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，耦合到NAND单元单元的一端的源极线以及耦合到另一端的位线 的NAND单元单元，其中NAND单元单元以如下的数据写入模式被偏置：将写入电压Vpgm施加到NAND单元单元中所选存储单元的控制栅极; 以特定数量的存储单元的间隔将通道隔离电压施加到设置在所选存储单元的源极侧的未选择存储单元的栅极; 并且将低于Vpgm的写入介质电压Vm施加到剩余的未选择存储单元的控制栅极。

公开(公告)号：US07405975B2

公开(公告)日：2008-07-29

申请号：US11485483

申请日：2006-07-13

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3454 ,  G11C2211/5621

摘要： A threshold voltage read method of a nonvolatile semiconductor memory device is disclosed. The threshold voltage read method applies a first threshold voltage measuring read voltage to the word line with a selection gate kept in a nonconductive state and then makes the selection gate conductive to read out a threshold voltage of the first data at the time of reading out the threshold voltage of the first data. Then, it applies a second threshold voltage measuring read voltage to the word line with the selection gate kept in the conductive state to read out a threshold voltage of the second data at the time of reading out the threshold voltage of the second data.

摘要翻译： 公开了一种非易失性半导体存储器件的阈值电压读取方法。 阈值电压读取方法将第一阈值电压测量读取电压施加到字线，其中选择栅极保持在非导通状态，然后使选择栅极导通以读出第一数据的阈值电压 第一数据的阈值电压。 然后，在读出第二数据的阈值电压时，将选择栅极保持导通状态的第二阈值电压测量读取电压施加到字线，以读出第二数据的阈值电压。