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    Method of programming a non-volatile memory device
    3.
    发明授权
    Method of programming a non-volatile memory device 有权
    编程非易失性存储器件的方法

    公开(公告)号：US07911823B2

    公开(公告)日：2011-03-22

    申请号：US12123827

    申请日：2008-05-20

    申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/12 ,  G11C8/08

    CPC分类号： G11C11/36

    摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

    摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US07817457B2

    公开(公告)日：2010-10-19

    申请号：US12132972

    申请日：2008-06-04

    申请人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohshima

    发明人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohshima

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/72

    摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

    摘要翻译： 根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

    METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE
    7.
    发明申请
    METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE 有权
    编程非易失性存储器件的方法

    公开(公告)号：US20080291716A1

    公开(公告)日：2008-11-27

    申请号：US12123827

    申请日：2008-05-20

    申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C11/00

    CPC分类号： G11C11/36

    摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

    摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

    NON-VOLATILE MEMORY DEVICE
    8.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号：US20090010039A1

    公开(公告)日：2009-01-08

    申请号：US12132972

    申请日：2008-06-04

    申请人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohsima

    发明人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohsima

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/72

    摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

    摘要翻译： 根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20070206399A1

    公开(公告)日：2007-09-06

    申请号：US11682478

    申请日：2007-03-06

    申请人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

    摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元 形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据 所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。