公开(公告)号：US11742042B2

公开(公告)日：2023-08-29

申请号：US17474539

申请日：2021-09-14

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Bueb ,  Poorna Kale

IPC: G11C29/02 ,  G06F11/07 ,  G06F11/30 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/406 ,  G11C7/04

CPC classification number: G11C29/028 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/3037 ,  G06F11/3058 ,  G11C7/04 ,  G11C11/4074 ,  G11C11/40626 ,  G11C11/5628

Abstract: A method comprising receiving, at a memory sub-system from a host system, receiving, at one or more configuration parameters reflecting an expected type of use of the memory sub-system; receiving one or more environmental parameters of the memory sub-system, wherein the environmental parameters reflect characteristics of an environment of the memory sub-system; and selecting a programming operation parameter to be utilized by the memory sub-system based on the configuration parameters and environmental parameters.

公开(公告)号：US20230266909A1

公开(公告)日：2023-08-24

申请号：US17652415

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for operating memory die based on temperature data are described. A memory system may include a set of temperature sensors each corresponding to one of a set of memory dies. A controller at the memory system may receive, from the set of temperature sensors, temperatures measured at the set of memory dies. Then the controller may identify that an operation of a first memory die is associated with an increased likelihood of errors based on the temperature measured at the first memory die. In response, the controller may adjust a parameter for operating the first memory die from a first value to a second value associated with a decreased operating temperature and operate the first memory die according to the second value of the parameter while operating one or more of the other memory dies in the set according to the first value of the parameter.

公开(公告)号：US11681903B2

公开(公告)日：2023-06-20

申请号：US16669902

申请日：2019-10-31

Applicant: Micron Technology, Inc.

Inventor： Anakha Vasanthakumaribabu ,  Poorna Kale

IPC: G06N3/063 ,  G11C13/00 ,  G06N3/049

CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C13/0026 ,  G11C13/0028

Abstract: Systems, methods and apparatus of implementing spiking neural networks. For example, an integrated circuit includes a crossbar array of first memristors connected between wordlines and bitlines. The first memristors are configured to convert voltages applied on the wordlines into currents in the bitlines. Second memristors having thresholds are connected to the bitlines respectively. Each respective memristor in the second memristors can reduce its resistance to cause spiking in a current flowing through the respective memristor, when the current reaches the threshold of the respective memristor. Current level detectors are connected to the second memristors to determine whether the currents in the bitlines have levels corresponding to reaching thresholds of the second memristors and thus, generate output spikes of spiking neurons without using analog-to-digital converters to measure the currents in the bitlines.

公开(公告)号：US11675498B2

公开(公告)日：2023-06-13

申请号：US17689858

申请日：2022-03-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Poorna Kale ,  Ashok Sahoo

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: One or more usage parameter values associated with a host system are obtained. The one or more parameter values correspond to one or more operations associated with a memory sub-system. An expected time period during which a set of host data will be received from the host system is determined in view of the one or more usage parameter values. In response to a determination, in view of an indication received from the host system, that the set of host data will not be received at the expected time period, a media management operation is performed at memory units of the memory sub-system.

公开(公告)号：US11663153B2

公开(公告)日：2023-05-30

申请号：US17326141

申请日：2021-05-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1605

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

公开(公告)号：US11573708B2

公开(公告)日：2023-02-07

申请号：US16452341

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G06F11/20

Abstract: A solid state drive having at least one component solid state drive, a spare solid state drive, and a drive aggregator. The drive aggregator has at least one host interface, at least one drive interface connected to the at least one component solid state drive, and an interface connected to the spare solid state drive. The drive aggregator is configured to maintain, in the spare solid state drive, a copy of a dataset that is stored in the component solid state drive. In response to a failure of the component solid state drive, the drive aggregator is configured to substitute a function of the component solid state drive with respect to the dataset with a corresponding function of the spare solid state drive, based on the copy of the dataset maintained in the spare solid state drive.

公开(公告)号：US20230004327A1

公开(公告)日：2023-01-05

申请号：US17899407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Robert Richard Noel Bielby ,  Poorna Kale

IPC: G06F3/06 ,  G06N3/04 ,  G06N3/08 ,  G06F12/10

Abstract: Systems, methods and apparatus of intelligent wear-leveling with reduced write-amplification for data storage devices configured on autonomous vehicles. For example, a data storage device of a vehicle includes: storage media components; a controller configured to store data into and retrieve data from the storage media components according to commands received in the data storage device; an address map configured to map between: logical addresses specified in the commands received in the data storage device, and physical addresses of memory cells in the storage media components; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized operation for wear leveling among memory cells in the data storage device. The controller is configured to perform the optimized operation for wear leveling based on the prediction.

公开(公告)号：US11544202B2

公开(公告)日：2023-01-03

申请号：US16658971

申请日：2019-10-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Bueb ,  Poorna Kale

IPC: G06F12/126 ,  G06F11/30 ,  G06F12/02 ,  G11C11/409 ,  G11C11/56 ,  G11C16/10

Abstract: A priority for each operating requirement of a set of operating requirements of a memory sub-system can be determined. A programming operation setting for a programming operation to be performed at the memory sub-system can be determined based on the priority for each operating requirement. A request to perform the programming operation at the memory sub-system can be received. Responsive to receiving the request to perform the programming operation, the programming operation can be performed at the memory sub-system based on the programming operation setting.

公开(公告)号：US20220383917A1

公开(公告)日：2022-12-01

申请号：US17887851

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: G11C7/10 ,  G06N3/08 ,  G06F7/544 ,  G06F17/16

Abstract: A dual-port, dual function memory device can be configured to perform operations on data written to the memory device using artificial intelligence (AI) circuitry, such as a neuromorphic array and/or a deep learning accelerator (DLA), of the memory device. The memory device can include a port dedicated for communication between the AI circuitry and a host device and another port dedicated for communication between a memory array of the memory device and a host device. Performing operations, such as image processing operations, using AI circuitry of a memory device can reduce data transfers, reduce resource consumption, and offload workloads from a host device.

公开(公告)号：US11507302B2

公开(公告)日：2022-11-22

申请号：US17235792

申请日：2021-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Poorna Kale

IPC: G06F3/06

Abstract: One or more programming operations are performed to program initial host data at the memory sub-system. The initial host data is received from a host system. A set of usage parameter values associated with the initial host data programmed at the memory sub-system is determined in view of the one or more programming operations. A media management operation is scheduled to be performed between a first time period and a second time period. The first time period corresponds to a time period during which the memory sub-system is expected to receive a first set of subsequent host data. The second time period corresponds to another time period during which the memory sub-system is expected to receive a second set of subsequent host data.