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    Non-volatile memory with extended error correction protection
    1.
    发明授权
    Non-volatile memory with extended error correction protection 有权
    具有扩展纠错保护功能的非易失性存储器

    公开(公告)号：US08495481B2

    公开(公告)日：2013-07-23

    申请号：US13684919

    申请日：2012-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Christopher Bueb

    IPC: G06F11/00

    CPC classification number: G06F11/10 ,  G06F11/1048 ,  G06F11/1068

    Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.

    Abstract translation: 本公开的实施例提供了与具有扩展的纠错保护的NVM设备相关的方法和装置。 在一些实施例中，奇偶校验高速缓存用于存储存储在NVM设备的多个码字中的数据值的奇偶校验值。 可以描述和要求保护其他实施例。

    Memory device using extended interface commands
    4.
    发明授权
    Memory device using extended interface commands 有权
    使用扩展接口命令的内存设备

    公开(公告)号：US09542121B2

    公开(公告)日：2017-01-10

    申请号：US14459171

    申请日：2014-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Christopher Bueb ,  Poorna Kale ,  Todd Legler

    IPC: G06F3/06 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/067 ,  G06F9/3004 ,  G06F9/30185 ,  G06F9/38

    Abstract: A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register.

    Abstract translation: 存储器件包括接收硬件可解码命令和扩展接口命令的串行接口缓冲器。 存储器装置还包括逻辑模块，其将硬件可解码命令引导到寄存器以供微控制器执行。 逻辑模块另外将扩展接口命令后接收的命令加载到子操作码寄存器中，其中逻辑模块在将扩展接口命令之后接收到的命令加载到子操作码寄存器之后保持被动。 还包括一个解释子操作码寄存器中的命令的微控制器。

    MULTILEVEL ENCODING WITH ERROR CORRECTION
    6.
    发明申请
    MULTILEVEL ENCODING WITH ERROR CORRECTION 有权
    多重编码与错误校正

    公开(公告)号：US20130024749A1

    公开(公告)日：2013-01-24

    申请号：US13627915

    申请日：2012-09-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Christopher Bueb

    IPC: H03M13/05

    CPC classification number: G06F11/1072 ,  G11C29/52

    Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed.

    Abstract translation: 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以通过改变多个存储单元的相应组的存储单元的逻辑电平来响应多个比特中的比特来将多个比特编码成多个存储单元。 可以描述和要求保护其他实施例。

    ADJUSTABLE MEMORY OPERATION SETTINGS BASED ON MEMORY SUB-SYSTEM OPERATING REQUIREMENTS
    7.
    发明申请
    ADJUSTABLE MEMORY OPERATION SETTINGS BASED ON MEMORY SUB-SYSTEM OPERATING REQUIREMENTS 有权

    公开(公告)号：US20230095179A1

    公开(公告)日：2023-03-30

    申请号：US18061850

    申请日：2022-12-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Christopher Bueb ,  Poorna Kale

    IPC: G06F12/126 ,  G06F12/02 ,  G11C11/409 ,  G11C11/56 ,  G06F11/30

    Abstract: A first set of memory access operations is performed at a memory sub-system based on first operation settings that are configured based on a first operating environment of a host system. A detection is made that the host system is operating in a second operating environment that is different from the first operating environment. A level of impact that each operating requirement of a set of operating requirements of the memory sub-system has on a performance of the memory sub-system in view of the second operating environment. A second set of memory access operations is determined based on a respective priority for each operating requirement of the set of operating requirements. A second set of memory access operations is performed at the memory sub-system based on the second set of memory access operation settings.

    Multilevel encoding with error correction
    9.
    发明授权
    Multilevel encoding with error correction 有权
    具有纠错的多级编码

    公开(公告)号：US09292383B2

    公开(公告)日：2016-03-22

    申请号：US14511102

    申请日：2014-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Christopher Bueb

    IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G11C29/52

    Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed.

    Abstract translation: 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，多个比特可以通过对多个比特的比特的多个多级存储器单元的子集进行电平移位来编码到多个存储器单元中。 可以描述和要求保护其他实施例。

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