公开(公告)号：US20060099245A1

公开(公告)日：2006-05-11

申请号：US10514674

申请日：2002-05-21

Applicant: Manoj Kumar ,  Naresh Talwar ,  Rajeev Raghuvanshi ,  Ashok Rampal

Inventor： Manoj Kumar ,  Naresh Talwar ,  Rajeev Raghuvanshi ,  Ashok Rampal

IPC: A61K9/48 ,  A61K9/64 ,  A61K9/22 ,  A61K31/403

CPC classification number: A61K9/0065 ,  A61K9/2866 ,  A61K9/4891

Abstract: The present invention relates to an oral drug delivery system with biphasic release characteristics comprising a porous matrix comprising at least one drug substance, sugar(s), a release retarding polymer, gas generating components and optionally, pharma-ceuti-cally acceptable auxiliary components wherein the pharmaceutical composition further comprises a coating of said drug substance. The pharmaceutical composi-tion, either in the form of pellets (multiparticulate or single unit dosage form), beads, granules, capsules or tablets, is retained in the stomach while selectively delivering the drug(s) at gastrointestinal levels and upper parts of the small intestine over an extended period of time. The release of the drug from the said pharmaceutical composition is characterized by a biphasic release profile of the drug substance, which exhibits both immediate and controlled release characteristics.

Abstract translation: 本发明涉及具有双相释放特征的口服药物递送系统，其包含多孔基质，其包含至少一种药物物质，糖，缓释聚合物，气体产生组分和任选的药物可接受的辅助成分，其中 药物组合物还包含所述药物的涂层。 以颗粒形式（多颗粒或单一单位剂型），珠粒，颗粒，胶囊或片剂的药物组合物保留在胃中，同时选择性地将药物在胃肠水平和 小肠在较长时间内。 药物从所述药物组合物的释放的特征在于药物物质的双相释放曲线，其表现出立即和控制释放特征。

公开(公告)号：US06673369B2

公开(公告)日：2004-01-06

申请号：US10054077

申请日：2002-01-22

Applicant: Ashok Rampal ,  Rajeev S. Raghuvanshi ,  Manoj Kumar

Inventor： Ashok Rampal ,  Rajeev S. Raghuvanshi ,  Manoj Kumar

IPC: A61K922

CPC classification number: A61K9/2054

Abstract: The present invention relates to a controlled release pharmaceutical composition comprising amounts ranging from about 0.1 to about 4.5% w/w, of one or more of rate controlling cellulosic ether polymers.

Abstract translation: 本发明涉及包含量为约0.1至约4.5％w / w的一种或多种速率控制纤维素醚聚合物的控释药物组合物。

公开(公告)号：US06358715B1

公开(公告)日：2002-03-19

申请号：US09205874

申请日：1998-12-04

Applicant: Manoj Kumar

Inventor： Manoj Kumar

IPC: C12P762

CPC classification number: C12P7/04 ,  C12N1/16

Abstract: The present invention provides for the production of ASA from yeast capable of producing ASA from KLG. The present invention provides methods for the production of ASA as well as recombinant yeast capable of producing ASA from a carbon source.

公开(公告)号：US06222752B1

公开(公告)日：2001-04-24

申请号：US09558603

申请日：2000-04-26

Applicant: Manoj Kumar ,  Huy Van Pham

Inventor： Manoj Kumar ,  Huy Van Pham

IPC: G11C1500

CPC classification number: G11C15/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses. The system further includes implementations for test mode, refill, ICACHE block invalidation and cache reset signal generation.

Abstract translation: 提供了一种用于实现有效地消除动态，高带宽高速缓存控制系统中出现的许多定时问题的高速缓存控制系统的方法和装置。 在一个示例性实施例中，提供了虚拟内容可寻址存储器（CAM）单元，并且策略性地放置在距离高速缓存字线驱动器电路最远的芯片布局上。 虚拟输出信号是高速缓存命中评估电路的所需输入，从而消除过早缓存命中输出。 虚拟单元被设计为当任何地址位线产生不匹配指示时，快速放电高速缓存匹配线并指示非命中状态，特别是对于扩展带宽和动态系统，其中地址线更广泛并且系统被同步到预定 时钟周期。 高速缓存系统进一步在预取模式下操作，以确定下一个在线请求的地址的命中。 该系统还包括用于测试模式，补充，ICACHE块无效和高速缓存重置信号生成的实现。

公开(公告)号：US6122710A

公开(公告)日：2000-09-19

申请号：US24806

申请日：1998-02-17

Applicant: Manoj Kumar ,  Huy Van Pham

Inventor： Manoj Kumar ,  Huy Van Pham

IPC: G06F12/08 ,  G11C11/413 ,  G11C15/00 ,  G11C15/04 ,  G06F12/00

CPC classification number: G11C15/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses. The system further includes implementations for test mode, refill, ICACHE block invalidation and cache reset signal generation.

Abstract translation: 提供了一种用于实现有效地消除动态，高带宽高速缓存控制系统中出现的许多定时问题的高速缓存控制系统的方法和装置。 在一个示例性实施例中，提供了虚拟内容可寻址存储器（CAM）单元，并且策略性地放置在距离高速缓存字线驱动器电路最远的芯片布局上。 虚拟输出信号是高速缓存命中评估电路的所需输入，从而消除过早缓存命中输出。 虚拟单元被设计为当任何地址位线产生不匹配指示时，快速放电高速缓存匹配线并指示非命中状态，特别是对于扩展带宽和动态系统，其中地址线更广泛并且系统被同步到预定 时钟周期。 高速缓存系统进一步在预取模式下操作，以确定下一个在线请求的地址的命中。 该系统还包括用于测试模式，补充，ICACHE块无效和高速缓存重置信号生成的实现。

公开(公告)号：US6104666A

公开(公告)日：2000-08-15

申请号：US329458

申请日：1999-06-10

Applicant: Manoj Kumar

Inventor： Manoj Kumar

IPC: G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/409 ,  G11C11/417 ,  G11C11/419 ,  G11C13/00 ,  G11C8/00

CPC classification number: G11C7/1078 ,  G11C11/419 ,  G11C7/12

Abstract: A write driver apparatus (10) is adapted for producing a first data output signal and a second data output signal used in driving data onto a bit line pair (16, 18) associated with an electronic computer memory. The first and second data output signals represent desired data and are produced in response to a data signal, refill signal, and a data propagation clock signal. The data propagation signal is derived from system clock signals. A precharge circuit (12) associated with the write driver (10) operates in response to a precharge clock signal to precharge the bit lines (16, 18) prior to each read or write operation. The precharge clock signal is related to the data propagation signal to ensure that the bit lines (16, 18) are fully precharged prior to a read operation. A keeper circuit (14) associated with the bit lines (16, 18) also helps maintain a desired charge state on the bit lines during a read operation from memory cells (20) connected to the bit lines.

Abstract translation: 写驱动器装置（10）适用于产生用于将数据驱动到与电子计算机存储器相关联的位线对（16,18）上的第一数据输出信号和第二数据输出信号。 第一和第二数据输出信号表示期望的数据，并且响应于数据信号，再填充信号和数据传播时钟信号产生。 数据传播信号来源于系统时钟信号。 与写入驱动器（10）相关联的预充电电路（12）响应于预充电时钟信号而工作，以在每次读或写操作之前对位线（16,18）进行预充电。 预充电时钟信号与数据传播信号相关，以确保位线（16,18）在读取操作之前被完全预充电。 与位线（16,18）相关联的保持器电路（14）还有助于在连接到位线的存储器单元（20）的读取操作期间在位线上保持期望的电荷状态。

公开(公告)号：US5796271A

公开(公告)日：1998-08-18

申请号：US929347

申请日：1997-08-26

Applicant: Manoj Kumar

Inventor： Manoj Kumar

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/24 ,  H03K19/003 ,  G11C8/00

CPC classification number: G11C29/84 ,  G11C29/02 ,  G11C29/24

Abstract: An address gating circuit for a memory array having redundant word lines. The address gating circuit includes a plurality of address lines comprising paired true and complement address lines for receiving address bits. The true and complement values of the address lines are ORed together then the results are ANDed together to generate an output. The output is used to inhibit selection of one of the address lines until a latest address bit is received.

Abstract translation: 一种具有冗余字线的存储器阵列的地址选通电路。 地址选通电路包括多个地址线，其包括用于接收地址位的成对的真和地址线。 地址线的真实值和补码值被OR整合在一起，然后将结果与“和”在一起以生成输出。 该输出用于禁止选择一个地址线，直到接收到最新的地址位。

公开(公告)号：US5615168A

公开(公告)日：1997-03-25

申请号：US538085

申请日：1995-10-02

Applicant: George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

Inventor： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1072

Abstract: A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.

Abstract translation: 用于提供组合同步和自复位技术的存储器系统的单时钟周期流水线访问的方法和装置包括排列成列和行并由位线和字线相互配合的存储器单元阵列。 存储器系统还包括地址解码器和感测使能电路。 地址解码器在接收到地址后，解释地址以启用特定字线或字线，并禁止位线或位线的预充电。 当字线有效时，当时钟信号遇到过渡沿或处于活动状态时，感测使能电路产生检测使能信号。 当感测使能信号有效时，读出放大器通过位线从寻址的存储单元读取数据，以产生输出数据。

公开(公告)号：US5568433A

公开(公告)日：1996-10-22

申请号：US491661

申请日：1995-06-19

Applicant: Manoj Kumar

Inventor： Manoj Kumar

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/24

CPC classification number: G11C29/84 ,  G11C29/02 ,  G11C29/24

Abstract: Multiselection of word lines is eliminated in a memory array which includes a word line generation circuit which inhibits line selection until a latest address bit is received.

Abstract translation: 在包括禁止行选择直到接收最新地址位的字线生成电路的存储器阵列中消除字线的多重选择。

公开(公告)号：US5544112A

公开(公告)日：1996-08-06

申请号：US457704

申请日：1995-06-02

Applicant: Manoj Kumar ,  Joseph M. Poplawski, Jr.

Inventor： Manoj Kumar ,  Joseph M. Poplawski, Jr.

IPC: G11C11/413 ,  G11C8/08 ,  G11C11/407 ,  G11C8/00 ,  H03K19/017

CPC classification number: G11C8/08

Abstract: A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.

Abstract translation: 字线驱动器电路，用于从解码器电路接收地址信号，并将这些地址信号选通作为字线信号输出到RAM内的一个或多个存储器单元。 驱动器电路通过不允许电路元件之间的任何内部节点具有浮动电位来防止输出的字线信号的振荡。 该功能由以独特方式布置的多个电路元件提供，使得内部节点不被允许浮动。