公开(公告)号：US06237066B1

公开(公告)日：2001-05-22

申请号：US09273850

申请日：1999-03-22

申请人： Bi-Yu Pan ,  Marc Tremblay

发明人： Bi-Yu Pan ,  Marc Tremblay

IPC分类号： G06F1202

CPC分类号： G06F9/3824

摘要： One embodiment of the present invention provides an apparatus that supports multiple outstanding load and/or store requests from an execution engine to multiple sources of data in a computer system. This apparatus includes a load store unit coupled to the execution engine, a first data source and a second data source. This load store unit includes a load address buffer, which contains addresses for multiple outstanding load requests. The load store unit also includes a controller that coordinates data flow between the load address buffer, a register file, the first data source and the second data source so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source. These load requests return in-order for each of the multiple sources of data in the computer system, except for load requests directed to a data cache which can return out-of-order. Load requests may return out-of-order with respect to load requests from other data sources. According to one aspect of the present invention, the load store unit additionally includes a store address buffer, that contains addresses for multiple outstanding store requests, and a store data buffer that contains data for the multiple outstanding store requests. The controller is further configured to coordinate data flow between the first data source, the second data source, the store address buffer and the store data buffer, so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source.

摘要翻译： 本发明的一个实施例提供了一种在计算机系统中支持来自执行引擎的多个未完成的负载和/或存储请求到多个数据源的装置。 该装置包括耦合到执行引擎的加载存储单元，第一数据源和第二数据源。 该加载存储单元包括加载地址缓冲器，其包含多个未完成的加载请求的地址。 加载存储单元还包括一个控制器，该控制器协调加载地址缓冲器，寄存器文件，第一数据源和第二数据源之间的数据流，使得多个加载请求可以同时对于第一数据源和第二数据都是突出的 资源。 这些加载请求在计算机系统中的多个数据源中的每一个都按顺序返回，除了指向可以无序返回的数据高速缓存的负载请求。 加载请求可能会与来自其他数据源的加载请求无关。 根据本发明的一个方面，加载存储单元还包括存储地址缓冲器，其包含多个未完成存储请求的地址，以及存储数据缓冲器，其包含多个未完成的存储请求的数据。 控制器还被配置为协调第一数据源，第二数据源，存储地址缓冲器和存储数据缓冲器之间的数据流，使得多个存储请求可以同时对于第一数据源和第二数据源都是突出的 。

公开(公告)号：US06233667B1

公开(公告)日：2001-05-15

申请号：US09263704

申请日：1999-03-05

申请人： Nik Shaylor ,  Jeffrey M. W. Chan ,  Gary R. Oblock ,  Marc Tremblay

发明人： Nik Shaylor ,  Jeffrey M. W. Chan ,  Gary R. Oblock ,  Marc Tremblay

IPC分类号： G06F1206

CPC分类号： G06F12/0292 ,  G06F12/0223 ,  G06F12/10 ,  G06F12/145

摘要： The present invention provides a method and an apparatus for translating a virtual address to a physical address in a computer system. The system receives a virtual address during an execution or a fetch of a program instruction. The system determines if the virtual address is in an upper portion or a lower portion of a virtual address space. If the virtual address is in the lower portion of the virtual address space, the system adds the virtual address to a first base address to produce the physical address. The system also compares the virtual address against an upper bound. If the virtual address has a larger value than the upper bound, the system indicates an illegal access. If the virtual address is in the upper portion of the virtual address space, the system adds the virtual address to a second base address to produce the physical address. The system also compares the virtual address against a lower bound. If the virtual address has a lower value than the lower bound, the system indicates that the access is illegal. Thus, the system provides protection from illegal memory accesses. According to one aspect of the present invention, the system determines if the virtual address falls within portion of the virtual address space that is protected from write accesses. If so, the system disallows write accesses to the virtual address. Thus, the present invention dispenses with paging and reduces the virtual-to-physical address translation process to a simple addition operation. This leads to faster processor clock speeds, and can greatly reduce the cost of designing and fabricating a computer system.

摘要翻译： 本发明提供了一种用于将虚拟地址翻译成计算机系统中的物理地址的方法和装置。 系统在执行或获取程序指令期间接收虚拟地址。 系统确定虚拟地址是否在虚拟地址空间的上部或下部。 如果虚拟地址在虚拟地址空间的较低部分，则系统将虚拟地址添加到第一个基地址以产生物理地址。 系统还将虚拟地址与上限进行比较。 如果虚拟地址的值比上限大，系统会指示非法访问。 如果虚拟地址在虚拟地址空间的上部，则系统将虚拟地址添加到第二个基地址以产生物理地址。 系统还将虚拟地址与下限进行比较。 如果虚拟地址的值低于下限，则表示该访问是非法的。 因此，系统提供防止非法内存访问的保护。 根据本发明的一个方面，系统确定虚拟地址是否落在防止写访问的虚拟地址空间的部分内。 如果是这样，系统不允许对虚拟地址进行写访问。 因此，本发明省去了寻呼，并将虚拟到物理地址转换过程减少到简单的附加操作。 这导致更快的处理器时钟速度，并且可以大大降低设计和制造计算机系统的成本。

公开(公告)号：US06230230B1

公开(公告)日：2001-05-08

申请号：US09204794

申请日：1998-12-03

申请人： William N. Joy ,  James M. O'Connor ,  Marc Tremblay

发明人： William N. Joy ,  James M. O'Connor ,  Marc Tremblay

IPC分类号： G06F1200

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087

摘要： Elimination of traps and atomics in thread synchronization is provided. In one embodiment, a processor includes a lock cache. The lock cache holds a value that corresponds to or identifies a computer resource only if a current thread executing on the processor owns the computer resource. A lock cache operation (e.g., a lockcachecheck instruction) determines whether a value identifying a computer resource is cached in the lock cache and returns a first predetermined value if the value identifying the computer resource is cached in the lock cache. Otherwise, a second predetermined value is returned.

摘要翻译： 提供线程同步中的陷阱和原子消除。 在一个实施例中，处理器包括锁高速缓存。 只有当处理器上执行的当前线程拥有计算机资源时，锁缓存才能保存对应于或识别计算机资源的值。 锁定高速缓存操作（例如，锁定检查指令）确定标识计算机资源的值是否被缓存在锁定缓存中，并且如果标识计算机资源的值被缓存在锁定缓存中，则返回第一预定值。 否则，返回第二预定值。

公开(公告)号：US6058457A

公开(公告)日：2000-05-02

申请号：US880934

申请日：1997-06-23

申请人： Marc Tremblay ,  James Michael O'Connor

发明人： Marc Tremblay ,  James Michael O'Connor

IPC分类号： G06F9/40 ,  G06F9/42 ,  G06F12/08

CPC分类号： G06F9/443 ,  G06F9/4425 ,  G06F2212/451

摘要： The present invention provides methods for storing method frames in a multi-stack memory architecture to provide access to multiple portions of the method frame. In one embodiment, a first frame component of a first method frame is stored in a first stack. A second component of the first method frame is stored in a second stack. A first component of a second method frame is stored in the second stack and a second frame component of the second method frame is stored in the first stack. In some embodiments, the first frame components of the first and second stacks are operand stacks, while the second frame components are arguments and local variable areas.

摘要翻译： 本发明提供了用于在多堆栈存储器架构中存储方法帧以提供对方法帧的多个部分的访问的方法。 在一个实施例中，第一方法帧的第一帧分量被存储在第一堆栈中。 第一方法框架的第二组件存储在第二堆栈中。 第二方法帧的第一分量被存储在第二堆栈中，并且第二方法帧的第二帧分量被存储在第一堆栈中。 在一些实施例中，第一和第二堆叠的第一帧组件是操作数堆栈，而第二帧组件是参数和局部可变区域。

公开(公告)号：US5925123A

公开(公告)日：1999-07-20

申请号：US787618

申请日：1997-01-23

申请人： Marc Tremblay ,  James Michael O'Connor

发明人： Marc Tremblay ,  James Michael O'Connor

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06F9/445 ,  G06F9/455 ,  G06F12/08 ,  G06F12/14 ,  G06F15/78

CPC分类号： G06F9/3822 ,  G06F12/0875 ,  G06F12/1441 ,  G06F15/7846 ,  G06F9/30021 ,  G06F9/30134 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/345 ,  G06F9/443 ,  G06F9/44589 ,  G06F9/45504 ,  G06F2212/451

摘要： A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

摘要翻译： 双指令集处理器解码并执行从网络接收的代码和从本地存储器提供的代码。 因此，双指令集处理器能够从两个不同的源执行两个不同指令集中的指令。 双指令集处理器包括独立于计算机平台的指令解码器，另一解码器和执行单元，其执行来自两个解码器的解码指令。 可以优化具有上述双指令集处理器，本地存储器和用于连接到诸如因特网或内部网的网络的诸如调制解调器的通信接口设备的计算机系统，以执行例如， 来自网络的一组独立于计算机平台的指令的例子中的JAVA代码，以及执行在本地存储的本地或在网络上存储的可信环境或授权环境中的非JAVA代码。

公开(公告)号：US5875483A

公开(公告)日：1999-02-23

申请号：US880253

申请日：1997-06-23

申请人： Marc Tremblay

发明人： Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F9/3836 ,  G06F9/30101 ,  G06F9/3857

摘要： A method and apparatus for generating a qualify bit and detecting matching addresses in the completion unit register file, or annex, of a processor. A qualify bit is appended to each entry in the annex. Overlapping register windows are represented by a window pointer and a register index. Annex entries addressed to the same window or addressed to GLOBAL registers always qualify. Annex entries addressed to OUT registers only qualify if the instruction address is one of the IN registers of the next window. Annex entries addressed to IN registers only qualify if the instruction address is one of the OUT registers of the previous window. A pseudo-address bit is appended to each annex entry. For IN and OUT registers, the indexes for the aliases differ by one bit. The pseudo-address bit normally takes on the value of the most significant bit of the annex entry's index. If the instruction operand virtual register is an OUT register of a certain window, and the annex virtual register is an IN register within the next window, the pseudo-address bit for that entry is set to one. If the instruction operand virtual register is an OUT register within the previous window, the pseudo-address bit for that entry is set to zero. Comparison logic then compares the instruction operand index to the annex index with the differing bit of the annex index replaced by the pseudo-address bit. Entries that match and that have asserted qualify bits address the same physical register.

摘要翻译： 一种用于生成限定位并检测处理器的完成单元寄存器文件或附件中的匹配地址的方法和装置。 附件中的每个条目附加有资格的位。 重叠寄存器窗口由窗口指针和寄存器索引表示。 寻址到同一个窗口或寻址到GLOBAL寄存器的附件条目始终符合条件。 寻址到OUT寄存器的附件条目仅限于指令地址是下一个窗口的IN寄存器之一。 寻址到IN寄存器的附件条目仅限于指令地址是上一窗口的OUT寄存器之一。 伪地址位附加到每个附件条目。 对于IN和OUT寄存器，别名的索引有所不同。 伪地址位通常取附件条目索引的最高有效位的值。 如果指令操作数虚拟寄存器是特定窗口的OUT寄存器，附件虚拟寄存器是下一个窗口中的IN寄存器，则将该条目的伪地址位设置为1。 如果指令操作数虚拟寄存器是上一个窗口内的一个OUT寄存器，则该条目的伪地址位设置为零。 比较逻辑然后将指令操作数索引与附件索引进行比较，附件索引的不同位由伪地址位替换。 符合条件的条目符合相同的物理寄存器。

公开(公告)号：US5873104A

公开(公告)日：1999-02-16

申请号：US882796

申请日：1997-06-26

申请人： Marc Tremblay ,  James Michael O'Connor ,  Guy L. Steele, Jr. ,  Sanjay Vishin ,  Ole Agesen ,  Steven Heller ,  Derek R. White

发明人： Marc Tremblay ,  James Michael O'Connor ,  Guy L. Steele, Jr. ,  Sanjay Vishin ,  Ole Agesen ,  Steven Heller ,  Derek R. White

IPC分类号： G06F12/00 ,  G06F9/44 ,  G06F12/02

CPC分类号： G06F12/0269 ,  G06F12/0276 ,  Y10S707/99957

摘要： A partially relocated object identifier store including "copy from" identifier and "copy to" identifier storage accessible to write barrier logic allows the write barrier logic to maintain consistency between FromSpace and ToSpace instances of a partially relocated memory object without software trap handler overhead. Optional "How far" indication storage facilitates differentiation by the write barrier logic between a copied portion and an uncopied portion of the partially relocated memory object. An optional "mode" indication facilitates differentiation by the write barrier logic between a copy phase and a pointer update phase of relocation by the garbage collector implementation. In some embodiments, pointer update and copying phases may overlap. "Copy to" identifier storage facilitates broadcast of a store-oriented memory access to the FromSpace instance to both FromSpace and ToSpace instances. Similarly, during pointer update, "Copy to" and "Copy From" identifier storage facilitate broadcast of a store-oriented memory access to either the FromSpace instance or the ToSpace instance to both FromSpace and ToSpace instances.

摘要翻译： 包含“复制”标识符和写入屏障逻辑可访问的“复制到”标识符存储的部分重新定位的对象标识符存储允许写入屏障逻辑在没有软件陷阱处理程序开销的情况下保持部分重新定位的存储器对象的FromSpace和ToSpace实例之间的一致性。 可选的“多远”指示存储有助于通过写入屏障逻辑在部分重定位的存储器对象的复制部分和未遮盖部分之间进行区分。 可选的“模式”指示有助于通过垃圾收集器实现的复制阶段和重新定位的指针更新阶段之间的写屏障逻辑的区分。 在一些实施例中，指针更新和复制阶段可以重叠。 “复制到”标识符存储便于将FromSpace实例的面向存储的存储器访问广播到FromSpace和ToSpace实例。 类似地，在指针更新期间，“复制到”和“复制自”标识符存储便于将FromSpace实例或ToSpace实例的面向存储的存储器访问广播到FromSpace和ToSpace实例。

公开(公告)号：US5611469A

公开(公告)日：1997-03-18

申请号：US429651

申请日：1995-04-27

申请人： Stanley Eiley ,  Marc Tremblay

发明人： Stanley Eiley ,  Marc Tremblay

IPC分类号： A47G25/14

CPC分类号： A47G25/1435

摘要： An identification clip for a garment hanger, wherein the garment hanger has a clip holder with a retaining pin and a flange spaced apart and parallel thereto forming a gap therebetween. The clip has side walls and a bight portion and the ends of the U forming a nip adapted to fit in the gap when the identification clip is on the retaining portion of the hanger so as to avoid easy removal of the clip from the hanger.

摘要翻译： 一种用于衣架的识别夹，其中所述衣架具有夹持器，所述夹持器具有保持销和间隔开并平行于其之间的间隔的凸缘。 夹具具有侧壁和弯曲部分，并且当识别夹位于衣架的保持部分上时，U形成适于装配在间隙中的压区的端部，以避免将夹子从挂钩中容易地移除。

公开(公告)号：US08898436B2

公开(公告)日：2014-11-25

申请号：US12426550

申请日：2009-04-20

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

摘要翻译： 在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。 解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。 具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。 第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

公开(公告)号：US20120331314A1

公开(公告)日：2012-12-27

申请号：US13529761

申请日：2012-06-21

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F1/32

CPC分类号： G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不物理地改变处理器周期或任何处理器供电电压。