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1.发明授权Logical power throttling of instruction decode rate for successive time periods 有权连续时间段的逻辑功率节制指令解码速率公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
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2.发明授权Start transactional execution (STE) instruction to support transactional program execution 有权启动事务执行（STE）指令以支持事务性程序执行公开(公告)号：US07500086B2
公开(公告)日：2009-03-03
申请号：US11296599
申请日：2005-12-06
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译： 本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。 在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。 在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。
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公开(公告)号：US07418577B2
公开(公告)日：2008-08-26
申请号：US10637169
申请日：2003-08-08
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
摘要翻译： 本发明的一个实施例提供一种支持执行失败指令的系统，其终止指令块的事务执行。 在操作期间，系统促进程序内的指令块的事务执行，其中在事务执行期间所做的更改不会被提交到处理器的体系结构状态，直到事务执行成功完成。 如果在此事务执行期间遇到失败指令，则系统终止事务执行，而不将事务执行的结果提交给处理器的体系结构状态。
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公开(公告)号：US20070226467A1
公开(公告)日：2007-09-27
申请号：US11425869
申请日：2006-06-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译： 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。
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公开(公告)号：US20120331314A1
公开(公告)日：2012-12-27
申请号：US13529761
申请日：2012-06-21
IPC分类号： G06F1/32
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不物理地改变处理器周期或任何处理器供电电压。
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6.发明授权公开(公告)号：US07818510B2
公开(公告)日：2010-10-19
申请号：US11832777
申请日：2007-08-02
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/467 , G06F12/0815
摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.
摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。
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7.发明授权Method and structure for explicit software control using scoreboard status information 有权使用记分牌状态信息显式软件控制的方法和结构公开(公告)号：US07711928B2
公开(公告)日：2010-05-04
申请号：US11082282
申请日：2005-03-16
IPC分类号： G06F9/30
CPC分类号： G06F9/30061 , G06F9/383 , G06F9/3838 , G06F9/3842
摘要： A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.
摘要翻译： 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。
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8.发明授权Method and apparatus for facilitating a fast restart after speculative execution 有权推测执行后促进快速重启的方法和装置公开(公告)号：US07469334B1
公开(公告)日：2008-12-23
申请号：US11095643
申请日：2005-03-30
IPC分类号： G06F9/44
CPC分类号： G06F9/3863 , G06F9/3867
摘要： One embodiment of the present invention provides a system that facilitates a fast execution restart following speculative execution. During normal operation of the system, a processor executes code on a non-speculative mode. Upon encountering a stall condition, the system checkpoints the state of the processor and executes the code in a speculative mode from the point of the stall. As the processor commences execution in speculative mode, it stores copies of instructions as they are issued into a recovery queue. When the stall condition is ultimately resolved, execution in non-speculative mode is recommenced and the execution units are initially loaded with instructions from the recovery queue, thereby avoiding the delay involved in waiting for instructions to propagate through the fetch and the decode stages of the pipeline. At the same time, the processor begins fetching subsequent instructions following the last instruction in the recovery queue. When all the instructions have been loaded from the recovery queue, the execution units begin receiving the subsequent instructions that have propagated through the fetch and decode stages of the pipeline.
摘要翻译： 本发明的一个实施例提供一种促进在推测执行之后的快速执行重新启动的系统。 在系统的正常操作期间，处理器以非推测模式执行代码。 在遇到停顿状态时，系统检查处理器的状态，并从失速点以推测模式执行代码。 当处理器以推测模式开始执行时，它会将指令的副本存储在恢复队列中。 当失速状态最终得到解决时，重新开始非推测模式的执行，并且执行单元最初被加载有来自恢复队列的指令，从而避免等待指令通过读取和解码阶段传播的延迟 管道。 同时，处理器开始在恢复队列中的最后一条指令之后提取后续指令。 当从恢复队列中加载所有指令时，执行单元开始接收通过流水线的读取和解码阶段传播的后续指令。
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9.发明授权Selectively unmarking load-marked cache lines during transactional program execution 有权在事务性程序执行期间选择性地取消标记加载标记的高速缓存行公开(公告)号：US07389383B2
公开(公告)日：2008-06-17
申请号：US11399049
申请日：2006-04-06
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。
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公开(公告)号：US07353363B2
公开(公告)日：2008-04-01
申请号：US11277716
申请日：2006-03-28
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/30196 , G06F9/328 , G06F9/382 , G06F9/3857 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a patchable and/or programmable decode mechanism can be efficiently provided. In some realizations, either (or both) predecode or (and) decode may be configured or reconfigured post-manufacture. In some realizations, either (or both) predecode or (and) decode may be configured at (or about) initialization. In some realizations, either (or both) predecode or (and) decode may be configured at run-time.
摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现，可以采用可配置的预解码机制来针对相应的指令模式在由处理器提供的固定解码和可编程解码路径之间进行选择。 以这种方式，可以有效地提供可修补和/或可编程的解码机制。 在一些实现中，可以在制造后配置或重新配置（或两者）预解码或（和）解码。 在某些实现中，可以在（或约）初始化时配置（或两者）预解码或（和）解码。 在某些实现中，可以在运行时配置（或两者）预解码或（和）解码。
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