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91.发明授权Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal receiving method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof 有权信号发送电路，信号接收电路，信号发送/接收电路，信号发送方法，信号接收方法，信号发送/接收方法，半导体集成电路及其控制方法
公开(公告)号：US6037816A
公开(公告)日：2000-03-14
申请号：US292381
申请日：1999-04-15
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
CPC分类号： H04L25/0292 , H04L25/0272 , H04L25/028
摘要： In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.
摘要翻译： 在基于电源电位传输具有极小振幅电压的第一对差分时钟信号UCLK，基于电源电位具有极小幅度电压的第二对差分时钟信号LCLK，LXCLK时， 作为信号接收电路的反相电路由CMOS反相电路构成。 构成CMOS反相电路的PMOS晶体管具有接收第一对差分时钟信号的栅电极和源电极。 构成CMOS反相电路的NMOS晶体管具有接收第二对差分时钟信号的栅电极和源电极。 当差分时钟信号的电位发生变化时，两个晶体管的各个栅极和源极之间的电位在相反的方向上移动，这确实切断晶体管。 因此，由反相电路构成的信号接收电路根据第一和第二对差分信号静态工作。
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公开(公告)号：US6028455A
公开(公告)日：2000-02-22
申请号：US994128
申请日：1997-12-19
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
CPC分类号： H04L25/0292 , H04L25/0272 , H04L25/028
摘要： In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.
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公开(公告)号：US5898735A
公开(公告)日：1999-04-27
申请号：US726225
申请日：1996-10-04
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
CPC分类号： H04L25/028 , H04L25/0272
摘要： Two multiplexors select a first signal Ain and its inverted signal /Ain in the first half of a single cycle of a clock signal and Ain and /Ain, i.e., a differential signal pair, are differential-transmitted to two signal lines. On the other hand, the two multiplexors select a second signal Bin and its inverted signal /Bin in the second half and Bin and /Bin, i.e., a differential signal pair, are differential-transmitted to the two signal lines. Based on the transition probability of Ain and Bin or based on the mode information of a system, either Ain or Bin is selected and is differential-transmitted. As a result of such arrangement, when the transmission of one of Ain and Bin is not required, the other signal can continuously be differential-transmitted using an unoccupied signal line, which makes it possible to increase the rate of signal transmission without having to increase the number of signal lines.
摘要翻译： 两个多路复用器在时钟信号的单个周期的前半部分和Ain和/ Ain（即差分信号对）中选择第一信号Ain及其反相信号/ Ain，差分发送到两条信号线。 另一方面，两个多路复用器选择第二信号Bin，并且其后半部分的反相信号/ Bin和Bin和/ Bin即差分信号对被差分发送到两条信号线。 基于Ain和Bin的转换概率，或者基于系统的模式信息，选择Ain或Bin进行差分发送。 作为这种安排的结果，当不需要Ain和Bin之一的传输时，可以使用未占用的信号线连续地进行差分发送，这使得可以增加信号传输的速率而不必增加 信号线的数量。
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公开(公告)号：US5859546A
公开(公告)日：1999-01-12
申请号：US744807
申请日：1996-11-06
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H03K19/00 , H03K19/096
CPC分类号： H03K19/00 , H03K19/096
摘要： An exclusive OR circuit is provided which detects whether or not a preceding-stage logical output value and a subsequent-stage logical output value agree. When these logical output values are found to agree, a NAND circuit functions to cut off the supply of a clock signal to a first and second switch circuits and to a latch circuit. Accordingly, when there occur no data changes between clock signal cycles, in a switch circuit and a latch circuit both arranged between each stage of a pipeline, the charge/discharge of the capacitance of gate electrodes of transistors forming these circuits is prevented, thereby reducing power consumption.
摘要翻译： 提供异或电路，其检测前级逻辑输出值和后级逻辑输出值是否一致。 当发现这些逻辑输出值一致时，NAND电路用于切断对第一和第二开关电路和锁存电路的时钟信号的供应。 因此，当在时钟信号周期之间没有发生数据变化时，在开关电路和两个布置在管线的每一级之间的锁存电路中，防止形成这些电路的晶体管的栅电极的电容的充电/放电，从而减少 能量消耗。
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95.发明授权Phase adjusting circuit, system including the same and phase adjusting method 失效相位调整电路，系统包括相位和相位调整方式
公开(公告)号：US5852380A
公开(公告)日：1998-12-22
申请号：US731437
申请日：1996-10-15
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
CPC分类号： H03K5/1508 , G06F1/10 , H03K5/133 , H03L7/0814
摘要： A phase adjusting circuit includes a circuit for providing an internal clock signal in synchronization with a reference clock signal, a delay circuit for delaying the internal clock signal for a predetermined delay time and an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time.
摘要翻译： 相位调整电路包括用于与基准时钟信号同步地提供内部时钟信号的电路，用于将内部时钟信号延迟预定延迟时间的延迟电路和用于调整参考时钟相位之间的相位差的调整部分 时钟信号和内部时钟信号的相位延迟了预定的延迟时间。
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96.发明授权Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time 失效单片图像数据存储系统和访问方法，利用多个存储体隐藏预充电时间
公开(公告)号：US5835952A
公开(公告)日：1998-11-10
申请号：US808938
申请日：1997-02-28
CPC分类号： G11C11/005 , G06F12/0607 , G09G5/399 , G11C7/1042 , G11C7/12 , G11C7/22
摘要： An image data memory with a 2-bank (bank A and bank B) structure is disclosed. The bank A stores only even field data, whereas the bank B stores only odd field data, and a peripheral circuit composed of elements such as row decoders and column decoders is provided in such a manner that each bank can be accessed independently of the other. One of the banks A and B is precharged while the other bank is accessed in order that the banks A and B are alternately accessed. Fast frame access is accomplished.
摘要翻译： 公开了一种具有2岸（银行A和银行B）结构的图像数据存储器。 存储体A只存储偶数场数据，而存储体B仅存储奇数场数据，并且以这样的方式提供由诸如行解码器和列解码器的元件组成的外围电路，使得可以独立于另一个存取存储体。 银行A和B之一被预先充电，而另一个银行被访问，以便银行A和B被交替访问。 完成快速帧访问。
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97.发明授权Static random access memory having variable supply voltages to the memory cells and method of operating thereof 失效具有对存储单元的可变电源电压的静态随机存取存储器及其操作方法
公开(公告)号：US5715191A
公开(公告)日：1998-02-03
申请号：US733313
申请日：1996-10-17
申请人： Hiroyuki Yamauchi , Toru Iwata
发明人： Hiroyuki Yamauchi , Toru Iwata
IPC分类号： G11C11/412 , G11C11/413
CPC分类号： G11C11/412
摘要： A memory cell includes a load transistor pair serving as a high data holding element, a drive transistor pair serving as a low data holding element, and an access transistor pair for accessing the high data holding element or the low data holding element. A high data holding potential corresponding to the source potential of the load transistor pair is set at a value larger than a supply potential, and a low data holding potential corresponding to the source potential of the drive transistor pair is set at a value larger than a ground potential. In a read operation, a source potential control line of a selected memory cell is connected with a ground line through a source line switch.
摘要翻译： 存储单元包括用作高数据保持元件的负载晶体管对，用作低数据保持元件的驱动晶体管对，以及用于访问高数据保持元件或低数据保持元件的存取晶体管对。 对应于负载晶体管对的源极电位的高数据保持电位被设置为大于电源电位的值，并且与驱动晶体管对的源极电位相对应的低数据保持电位被设置为大于 地电位。 在读取操作中，所选存储单元的源极电位控制线通过源极线开关与地线连接。
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公开(公告)号：US5638013A
公开(公告)日：1997-06-10
申请号：US458654
申请日：1995-06-02
申请人： Toru Iwata , Hiroyuki Yamauchi
发明人： Toru Iwata , Hiroyuki Yamauchi
摘要： In a signal transmission circuit having a plurality of signal lines for supplying potentials to load capacitances, in which each load capacitance is driven by each signal line, each signal line can be connected to another signal line via a switch. By connecting two signal lines at different potentials to each other by means of said switch, the potentials of the signal lines are changed through the process of charge redistribution, thereby eliminating charging and discharging through a power-source line and a ground line. Therefore, if n load capacitances are equal to each other, the switches are controlled so that the potential variation of each of the signal lines is phase shifted from those of its adjacent signal lines by 1/n. Thus, the load capacitances can be driven with 1/n of the total amount of charge consumed in the case of driving the n load capacitances independently, thereby reducing the consumed current.
摘要翻译： 在具有用于提供负载电容的电位的多条信号线的信号传输电路中，每个负载电容由每个信号线驱动，每个信号线可以经由开关连接到另一条信号线。 通过利用所述开关将两个不同电位的信号线彼此连接，通过电荷重新分配的过程改变信号线的电位，从而消除通过电源线和接地线的充电和放电。 因此，如果n个负载电容彼此相等，则控制开关，使得每个信号线的电位变化与其相邻信号线的电位变化相位移1 / n。 因此，在驱动n个负载电容的情况下，可以以消耗的总电量的1 / n为1 / n来驱动负载电容，从而降低消耗电流。
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公开(公告)号：US5594701A
公开(公告)日：1997-01-14
申请号：US420875
申请日：1995-04-13
申请人： Hideo Asaka , Hiroyuki Yamauchi
发明人： Hideo Asaka , Hiroyuki Yamauchi
IPC分类号： G11C8/08 , G11C11/408 , G11C11/4094 , G11C29/02 , G11C29/50 , G11C8/00 , G11C29/00
CPC分类号： G11C11/4094 , G11C11/4085 , G11C29/02 , G11C29/50 , G11C8/08 , G11C11/401
摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another valve during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.
摘要翻译： 当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。 当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。 在将上述公共电源线连接到地面的路径中设置有阻抗改变装置，用于改变在待机期间的值与操作期间的另一个阀之间的路径的阻抗，在此期间选择任何字线，使得待机期间的值为 设置高于操作期间的值。 因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。
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公开(公告)号：US5508963A
公开(公告)日：1996-04-16
申请号：US209120
申请日：1994-03-11
申请人： Akihiro Sawada , Hiroyuki Yamauchi , Hironori Akamatsu , Shunichi Iwanari , Masashi Agata , Hirohito Kikukawa , Hisakazu Kotani
发明人： Akihiro Sawada , Hiroyuki Yamauchi , Hironori Akamatsu , Shunichi Iwanari , Masashi Agata , Hirohito Kikukawa , Hisakazu Kotani
CPC分类号： G11C29/785 , G11C29/80 , G11C29/808 , G11C29/83 , G11C29/84 , G11C29/846
摘要： N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.
摘要翻译： N段冗余地址比较电路分别由阻抗转换电路组成，从而使用冗余的信息作为阻抗值传输。 因此，即使当存储器的容量变大时N变大，具有大电容的信号线和冗余判断电路的节点也不被充电或放电。 可以实现高速操作，而不受信号线的电容或冗余判断电路的节点的电容的影响。
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