公开(公告)号：US5508963A

公开(公告)日：1996-04-16

申请号：US209120

申请日：1994-03-11

申请人： Akihiro Sawada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Shunichi Iwanari ,  Masashi Agata ,  Hirohito Kikukawa ,  Hisakazu Kotani

发明人： Akihiro Sawada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Shunichi Iwanari ,  Masashi Agata ,  Hirohito Kikukawa ,  Hisakazu Kotani

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  G11C29/83 ,  G11C29/84 ,  G11C29/846

摘要： N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

摘要翻译： N段冗余地址比较电路分别由阻抗转换电路组成，从而使用冗余的信息作为阻抗值传输。 因此，即使当存储器的容量变大时N变大，具有大电容的信号线和冗余判断电路的节点也不被充电或放电。 可以实现高速操作，而不受信号线的电容或冗余判断电路的节点的电容的影响。

公开(公告)号：US5818782A

公开(公告)日：1998-10-06

申请号：US814507

申请日：1997-03-10

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C13/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5719531A

公开(公告)日：1998-02-17

申请号：US739841

申请日：1996-10-30

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03F3/45

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5642323A

公开(公告)日：1997-06-24

申请号：US573076

申请日：1995-12-15

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

公开(公告)号：US5680366A

公开(公告)日：1997-10-21

申请号：US573133

申请日：1995-12-15

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03K3/26

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

公开(公告)号：US5515334A

公开(公告)日：1996-05-07

申请号：US260922

申请日：1994-06-15

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5546346A

公开(公告)日：1996-08-13

申请号：US354124

申请日：1994-12-06

申请人： Masashi Agata ,  Kazuhiro Matsuyama ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

发明人： Masashi Agata ,  Kazuhiro Matsuyama ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.

摘要翻译： 在需要与时钟信号同步执行高速连续操作的同步DRAM中，DBI线对连接在DQ线对和RDB线对之间，其流水线操作的单周期时间为 分为四个阶段。 该S-DRAM具有以下：第一预充电电路，用于仅在第一和第四周期中将DQ线对预充电或电压均衡至电源电压电平; 第二预充电电路，用于仅在第一和第二周期中将DBI线对对电压均衡至接地电压电平; 第三预充电电路，用于仅在第一和第二周期中将RDB线对对电压均衡至电源电压电平; 第一和第二差分放大器，用于在第三周期中将DQ线上的数据发送到DBI线上，并且用于在第四周期中将数据保存在DBI线上; 以及第三差分放大器，其在第三周期中将DBI线上的数据发送到RDB线上，并且在第四周期中将数据保存在RDB线上。

公开(公告)号：US5426601A

公开(公告)日：1995-06-20

申请号：US184933

申请日：1994-01-24

申请人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

发明人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/143

摘要： An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.

摘要翻译： 外部电源电压VCC作为第一内部电源电压VPERI施加到外围电路。 如果VCC在VCC推荐工作条件下规定的电压范围内VCC不大于下限电压V0L，则电源电压控制电路输出高逻辑电平的电压控制信号VSIG，否则输出低逻辑电平的VSIG。 电源电路将第二内部电源电压VW和第三内部电源电压VWORD施加到存储单元部分。 如果VSIG为高电平，则VW等于VPERI，而另一方面，VW是VPERI升压的电压。 VWORD是由于将VW进一步升高而产生的电压。 行解码器将VW发送到一行读出放大器的使能信号线上，并将VWORD发送到存储单元阵列的字线上，以使VW成为存储单元的高逻辑电平数据写入电压。 这样就可以在不牺牲存储单元耐压的情况下充分延长数据保持时间。

公开(公告)号：US5396124A

公开(公告)日：1995-03-07

申请号：US128726

申请日：1993-09-30

申请人： Akihiro Sawada ,  Hiroyuki Yamauchi

发明人： Akihiro Sawada ,  Hiroyuki Yamauchi

IPC分类号： G11C29/00 ,  H03K19/003

CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/83 ,  G11C29/84 ,  G11C29/846

摘要： In a semiconductor memory having a redundant circuit, a plurality of first normal cells and a plurality of first spare cells are connected to a first pair of data lines, and a plurality of second normal cells and a plurality of second spare cells are connected to a second pair of data lines. Both pairs of data lines are connected to an output data line through a selecting amplifier. A normal cell is selected based on a combination of NGWL1, NGWL2, . . . with BLK1, BLK2, both NGWL1, NGWL2, . . . and BLK1, BLK2 being supplied from a decoder, and a spare cell is selected based on a combination of the BLK1, BLK2 supplied from the decoder with SGWL1, SGWL2, . . . supplied from a redundancy judging circuit. A second spare cell is selected when a first normal cell is selected, and a first spare cell is selected when a second normal cell is selected. Only at the time when a spare address is entered, one of the SGWL1, SGWL 2, . . . is raised. This not only achieves a high-speed reading and a high defect-relief rate, but also reduces the current consumption and the chip area.

摘要翻译： 在具有冗余电路的半导体存储器中，多个第一正常单元和多个第一备用单元连接到第一对数据线，并且多个第二正常单元和多个第二备用单元连接到 第二对数据线。 两对数据线通过选择放大器连接到输出数据线。 基于NGWL1，NGWL2的组合选择正常单元格。 。 。 与BLK1，BLK2，NGWL1，NGWL2，。 。 。 并且从解码器提供BLK1，BLK2，并且基于从解码器提供的BLK1，BLK2与SGWL1，SGWL2组合来选择备用单元。 。 。 从冗余判断电路提供。 当选择第一正常小区时选择第二备用小区，并且当选择第二正常小区时选择第一备用小区。 只有在输入备用地址时，SGWL1，SGWL 2， 。 。 被提高 这不仅实现了高速读数和高缺陷缓解率，而且降低了电流消耗和芯片面积。

公开(公告)号：US20070001547A1

公开(公告)日：2007-01-04

申请号：US11476057

申请日：2006-06-28

申请人： Akihiro Sawada

发明人： Akihiro Sawada

IPC分类号： H01L41/09

CPC分类号： G04C3/12 ,  G04C17/0058 ,  H02N2/0025 ,  H02N2/004 ,  H02N2/026 ,  H02N2/062 ,  H02N2/103 ,  H02N2/142

摘要： To provide a drive detection means for a piezoelectric actuator that can detect an amount driven without requiring adding an encoder or other component while also preventing increasing the load. A rotor is disposed eccentrically to the axis of rotation to change the pressure applied from the rotor to a contact part as the rotor is driven. When the pressure changes, the amplitude of the detection signal output from the detection electrode 18 of the piezoelectric element changes in conjunction with rotor rotation, and how much the rotor has been driven can be detected by detecting the amplitude change. Size and thickness can therefore be reduced because providing an encoder, switch, or other component is unnecessary, and current consumption can also be reduced.

摘要翻译： 提供一种用于压电致动器的驱动检测装置，该驱动器检测装置可以在不需要增加编码器或其他部件的同时也可以检测驱动量，同时也防止增加负载。 当转子被驱动时，转子偏心地设置在旋转轴上，以将从转子施加的压力改变为接触部分。 当压力变化时，从压电元件的检测电极18输出的检测信号的振幅与转子旋转一起变化，并且可以通过检测振幅变化来检测转子多少。 因此，由于不需要提供编码器，开关或其他部件，因此可以减小尺寸和厚度，并且还可以减少电流消耗。