公开(公告)号：US08363445B2

公开(公告)日：2013-01-29

申请号：US13283267

申请日：2011-10-27

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US20120273894A1

公开(公告)日：2012-11-01

申请号：US13094873

申请日：2011-04-27

申请人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

发明人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/7843

摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

摘要翻译： 集成电路结构在衬底上包括至少一对互补晶体管。 一对互补晶体管包括第一晶体管和第二晶体管。 此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。 第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。 第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

公开(公告)号：US20120217613A1

公开(公告)日：2012-08-30

申请号：US13466986

申请日：2012-05-08

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

摘要翻译： 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

公开(公告)号：US08062951B2

公开(公告)日：2011-11-22

申请号：US11953445

申请日：2007-12-10

申请人： Xiangdong Chen ,  Kenneth J. Stein ,  Thomas A. Wallner

发明人： Xiangdong Chen ,  Kenneth J. Stein ,  Thomas A. Wallner

IPC分类号： H01L29/76

CPC分类号： H01L21/76232 ,  H01L29/66651

摘要： An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.

摘要翻译： 硅（Si）或硅锗（SiGe）的外延层在硅沟槽隔离（STI）的边缘上延伸，从而增加由STI界定的有源硅区域（RX）的有效宽度。 RX区域可以具有<100>晶体取向。 可以增加在RX区域中形成的FET器件的有效宽度，因此可以以相同的密度提高性能。 隔离可能不会降低，因为RX至RX距离在底部相同。 由于RX的一部分在STI上，结电容可能会降低。

公开(公告)号：US08003454B2

公开(公告)日：2011-08-23

申请号：US12125855

申请日：2008-05-22

申请人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

发明人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

IPC分类号： H01L21/336 ,  H01L21/337

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

摘要翻译： 半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34） 以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积 接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

公开(公告)号：US20110108903A1

公开(公告)日：2011-05-12

申请号：US12590370

申请日：2009-11-06

申请人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

发明人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

摘要翻译： 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20110107192A1

公开(公告)日：2011-05-05

申请号：US11908251

申请日：2006-01-03

申请人： Shuzhi Ge ,  Xiangdong Chen ,  Xiaoyan Han

发明人： Shuzhi Ge ,  Xiangdong Chen ,  Xiaoyan Han

IPC分类号： G06F17/00

CPC分类号： A61K31/12

摘要： An authoring tool for creating an electronic document, a method for creating the electronic document, a data storage medium for instructing a computer to execute the method for creating the electronic document and a data storage medium for instructing a computer to display the electronic document. The authoring tool comprises; a template module for selecting a template for the electronic document, the template comprising one or more display pages; a content management module for arranging one or more media files on each display page with selected interrelationships between the media files; a generating module for creating an electronic page file for each display page, wherein the media files are embedded in the respective electronic page files based on the selected interrelationships and in a manner such that each electronic page file includes interrelationship data defining the interrelationships of the embedded media files in said each electronic page file with other media files in said each electronic page file and with other media files in other electronic page files of the electronic document; and a binding module for electronically binding the respective electronic page files so as to create the electronic document.

摘要翻译： 用于创建电子文档的创作工具，用于创建电子文档的方法，用于指示计算机执行创建电子文档的方法的数据存储介质和用于指示计算机显示电子文档的数据存储介质。 创作工具包括 用于选择所述电子文档的模板的模板模块，所述模板包括一个或多个显示页面; 内容管理模块，用于在每个显示页面上布置一个或多个媒体文件，其中媒体文件之间具有选定的相互关系; 用于为每个显示页面创建电子页面文件的生成模块，其中基于所选择的相互关系将媒体文件嵌入在相应的电子页面文件中，并且以这样的方式使得每个电子页面文件包括定义嵌入的相互关系的相互关系数据 所述每个电子页面文件中的媒体文件与所述每个电子页面文件中的其他媒体文件以及电子文档的其他电子页面文件中的其他媒体文件; 以及用于电子地绑定各个电子页面文件以便创建电子文档的装订模块。

公开(公告)号：US20110089490A1

公开(公告)日：2011-04-21

申请号：US12589357

申请日：2009-10-21

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20110037144A1

公开(公告)日：2011-02-17

申请号：US12583016

申请日：2009-08-13

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L28/90 ,  H01L29/94 ,  H01L29/945

摘要： According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

摘要翻译： 根据示例性实施例，在晶片中制造去耦复合电容器的方法包括覆盖在衬底上的电介质区域包括在电介质区域和衬底中形成贯通晶片通孔。 贯通晶片通孔包括覆盖贯通晶片通孔开口的侧壁和底部的贯通晶片通孔绝缘体，以及通过绝缘体覆盖贯通晶片的贯通晶片通孔导体。 该方法还包括使衬底变薄，形成衬底背面绝缘体，在衬底背面绝缘体中形成开口以通过导体暴露通过晶片，以及通过导体在透晶片上形成背面导体，使得衬底背侧导体 延伸到衬底背面绝缘体上，从而形成去耦复合电容器。 衬底形成第一去耦合复合电容器电极，并且通过晶片通孔导体和衬底背侧导体形成第二去耦复合电容器电极。

公开(公告)号：US20100284210A1

公开(公告)日：2010-11-11

申请号：US12387573

申请日：2009-05-05

申请人： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

发明人： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的单元晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 单元晶体管具有源极，栅极和与之短接在一起的主体。 响应于位线和字线上的编程电压，编程操作导致在单元晶体管的源极和漏极之间发生穿透。 单元晶体管的沟道长度基本上小于存取晶体管的沟道长度。 在一个实施例中，存取晶体管是NFET，而单元晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，单元晶体管也是NFET。 各种实施例导致所需编程电压的降低。