公开(公告)号：US10529403B2

公开(公告)日：2020-01-07

申请号：US16159049

申请日：2018-10-12

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US20200005839A1

公开(公告)日：2020-01-02

申请号：US16512999

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US10424360B2

公开(公告)日：2019-09-24

申请号：US16032398

申请日：2018-07-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/00 ,  G11C11/56

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US10395717B2

公开(公告)日：2019-08-27

申请号：US16030590

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US20190189190A1

公开(公告)日：2019-06-20

申请号：US15845619

申请日：2017-12-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Lucia Di Martino

IPC: G11C11/4091 ,  G11C11/4074

Abstract: Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.

公开(公告)号：US10163482B2

公开(公告)日：2018-12-25

申请号：US15855326

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US20180336941A1

公开(公告)日：2018-11-22

申请号：US16030590

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2275

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US10049713B2

公开(公告)日：2018-08-14

申请号：US15246249

申请日：2016-08-24

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US09225334B2

公开(公告)日：2015-12-29

申请号：US14299693

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Marco Sforzin

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/018528 ,  H03K19/00

Abstract: Buffers, integrated circuits, apparatuses, and methods for adjusting drive strength of a buffer are disclosed. In an example apparatus, the buffer includes a driver. The driver includes a pull-up circuit coupled to a supply voltage node and an output node, and also includes a pull-down circuit coupled to a reference voltage node and the output node. A drive adjust circuit is coupled to at least one of the pull-up circuit and the pull-down circuit, with the drive adjust circuit configured to receive a feedback signal and, based at least in part on the feedback signal, adjust a current conducted through the at least one of the pull-up and pull-down circuits.

Abstract translation: 公开了用于调节缓冲器的驱动强度的缓冲器，集成电路，装置和方法。 在示例性装置中，缓冲器包括驱动器。 驱动器包括耦合到电源电压节点和输出节点的上拉电路，并且还包括耦合到参考电压节点和输出节点的下拉电路。 驱动调节电路被耦合到上拉电路和下拉电路中的至少一个，驱动调整电路被配置为接收反馈信号，并且至少部分地基于反馈信号调整传导的电流 通过上拉和下拉电路中的至少一个。

公开(公告)号：US09087583B2

公开(公告)日：2015-07-21

申请号：US14325075

申请日：2014-07-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Di Vincenzo ,  Carlo Lisi

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/009

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract translation: 本文公开的主题涉及存储器件，更具体地，涉及对存储器单元的编程。