中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

153 records (took 0.023 seconds)

    Voltage adjustment based on pending refresh operations
    91.
    发明授权
    Voltage adjustment based on pending refresh operations 有权

    公开(公告)号：US11568913B2

    公开(公告)日：2023-01-31

    申请号：US17164738

    申请日：2021-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

    IPC: G11C11/406

    Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

    MEMORY WITH PARTIAL ARRAY REFRESH
    95.
    发明申请
    MEMORY WITH PARTIAL ARRAY REFRESH 有权

    公开(公告)号：US20220189540A1

    公开(公告)日：2022-06-16

    申请号：US17684235

    申请日：2022-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

    Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

    MANAGEMENT OF HEAT ON A SEMICONDUCTOR DEVICE AND METHODS FOR PRODUCING THE SAME
    97.
    发明申请
    MANAGEMENT OF HEAT ON A SEMICONDUCTOR DEVICE AND METHODS FOR PRODUCING THE SAME 有权

    公开(公告)号：US20220093488A1

    公开(公告)日：2022-03-24

    申请号：US17030144

    申请日：2020-09-23

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

    IPC: H01L23/467 ,  H01L25/00 ,  H01L25/10

    Abstract: An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.

    Apparatuses and methods for staggered timing of targeted refresh operations
    98.
    发明授权
    Apparatuses and methods for staggered timing of targeted refresh operations 有权

    公开(公告)号：US11222683B2

    公开(公告)日：2022-01-11

    申请号：US17008396

    申请日：2020-08-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： James S. Rehmeyer

    IPC: G11C11/406 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408

    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. Memory dies may need to periodically perform refresh operations, which may be auto-refresh operations or targeted refresh operations. Targeted refresh operations may draw less current than auto-refresh operations. When dies are collected into a group (e.g., a memory stack, a memory module) the timing of targeted refresh operations may be staggered between the different dies to help reduce the peak current drawn. The targeted refresh operations may be staggered such that, when a maximum number of the dies are performing a refresh operation, at least one of the dies performs a targeted refresh operation instead of an auto-refresh operation.

    MEMORY WITH PER DIE TEMPERATURE-COMPENSATED REFRESH CONTROL
    99.
    发明申请
    MEMORY WITH PER DIE TEMPERATURE-COMPENSATED REFRESH CONTROL 有权

    公开(公告)号：US20220005523A1

    公开(公告)日：2022-01-06

    申请号：US16921729

    申请日：2020-07-06

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

    IPC: G11C11/406 ,  G06F11/30

    Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

Patent Agency Ranking