公开(公告)号：US20200371870A1

公开(公告)日：2020-11-26

申请号：US16989478

申请日：2020-08-10

申请人： Micron Technology, Inc.

发明人： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Ravaprolu ,  Ashutosh Malshe

IPC分类号： G06F11/10 ,  G06F11/14

摘要： A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US20200371690A1

公开(公告)日：2020-11-26

申请号：US16947713

申请日：2020-08-13

申请人： Micron Technology, Inc.

发明人： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Harish R. Singidi ,  Ashutosh Malshe ,  Kishore Kumar Muchherla

IPC分类号： G06F3/06

摘要： A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.

公开(公告)号：US10755793B2

公开(公告)日：2020-08-25

申请号：US15799655

申请日：2017-10-31

申请人： Micron Technology, Inc.

发明人： Harish Singidi ,  Scott Stoller ,  Jung Sheng Hoei ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Kishore Kumar Muchherla

IPC分类号： G11C16/34 ,  G11C16/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

摘要： NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

公开(公告)号：US10719271B2

公开(公告)日：2020-07-21

申请号：US16193126

申请日：2018-11-16

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Karl D. Schuh ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam ,  Harish Reddy Singidi ,  Renato Padilla, Jr.

IPC分类号： G11C7/04 ,  G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

摘要： Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

公开(公告)号：US10672452B2

公开(公告)日：2020-06-02

申请号：US16138115

申请日：2018-09-21

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC分类号： G11C7/00 ,  G11C11/406 ,  G06F13/16

摘要： Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.

公开(公告)号：US10586602B2

公开(公告)日：2020-03-10

申请号：US16436567

申请日：2019-06-10

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC分类号： G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02 ,  G11C16/24 ,  G11C16/08

摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20200020407A1

公开(公告)日：2020-01-16

申请号：US16448502

申请日：2019-06-21

申请人： Micron Technology, Inc.

发明人： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC分类号： G11C16/26

摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US10365854B1

公开(公告)日：2019-07-30

申请号：US15924951

申请日：2018-03-19

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Sampath Ratnam ,  Harish Singidi ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F3/06

摘要： A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10340016B2

公开(公告)日：2019-07-02

申请号：US15633377

申请日：2017-06-26

申请人： Micron Technology, Inc.

发明人： Renato C. Padilla ,  Jung Sheng Hoei ,  Michael G. Miller ,  Roland J. Awusie ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Gary F. Besinga ,  Ashutosh Malshe ,  Harish R. Singidi

IPC分类号： G11C16/34 ,  G11C11/56

摘要： A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

公开(公告)号：US20190066739A1

公开(公告)日：2019-02-28

申请号：US15692407

申请日：2017-08-31

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC分类号： G11C7/10 ,  G11C8/10

CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C29/023 ,  G11C29/028 ,  G11C2216/14 ,  G11C2216/22

摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.