公开(公告)号：US11269553B2

公开(公告)日：2022-03-08

申请号：US16878304

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, Jr. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/34

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US11126495B2

公开(公告)日：2021-09-21

申请号：US15914858

申请日：2018-03-07

Applicant: Micron Technology, Inc.

Inventor： Renato Padilla, Jr. ,  Gary F. Besinga ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/07 ,  G06F11/30

Abstract: A system configured to determine that a trigger condition has occurred that is related to an operation performed on a memory device of the system. Responsive to determining that the trigger condition has occurred, reordering error handling mechanisms of an error handling sequence based upon an error handling mechanism performance metric. Each error handling mechanism specifies operations to be performed to recover an error in the operation on the memory device.

公开(公告)号：US10998034B2

公开(公告)日：2021-05-04

申请号：US17017201

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C7/04 ,  G11C11/406 ,  G06F13/16

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US10915395B2

公开(公告)日：2021-02-09

申请号：US16193171

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Xiangang Luo ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Sampath Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.

公开(公告)号：US10719271B2

公开(公告)日：2020-07-21

申请号：US16193126

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Karl D. Schuh ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam ,  Harish Reddy Singidi ,  Renato Padilla, Jr.

IPC: G11C7/04 ,  G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

公开(公告)号：US10672452B2

公开(公告)日：2020-06-02

申请号：US16138115

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C7/00 ,  G11C11/406 ,  G06F13/16

Abstract: Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.

公开(公告)号：US11709633B2

公开(公告)日：2023-07-25

申请号：US17685102

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, Jr. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/3422

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US11024394B2

公开(公告)日：2021-06-01

申请号：US16844269

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Harish Singidi ,  Kishore Muchherla ,  Ashutosh Malshe ,  Vamsi Rayaprolu ,  Sampath Ratnam ,  Renato Padilla, Jr. ,  Michael Miller

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C7/10 ,  G11C7/04 ,  G11C29/42

Abstract: A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.

公开(公告)号：US10691377B2

公开(公告)日：2020-06-23

申请号：US16138334

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, Jr. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/34

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US10579307B2

公开(公告)日：2020-03-03

申请号：US16566545

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Sampath Ratnam ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Peter Sean Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/08

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.